(54) RAISED SILICIDE SOURCE/DRAIN MOS TRANSISTORS HAVING ENLARGED SOURCE/DRAIN CONTACT REGIONS AND METHOD
(75) Inventors: Keizo Sakiyama, Kashihara (JP);
Sheng Teng Hsu, Camas, WA (US)
(73) Assignee: Sharp Laboratories of America, Inc.,
Camas, WA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/497,626
(22) Filed: Feb. 3, 2000
(51) Int. CI.7 H01L 21/336
(52) U.S. CI 438/300; 438/596; 438/633;
438/683
(58) Field of Search 438/300, 304,
438/595, 596, 633, 634, 683
(56) References Cited
U.S. PATENT DOCUMENTS
4,471,522 A 9/1984 Jambotkar 29/571
5,376,578 A 12/1994 Hsu et al 437/56
5,491,099 A 2/1996 Hsu 437/35
5,516,710 A 5/1996 Boyd et al 437/31
5,683,924 A * 11/1997 Chan et al 438/300
5,773,358 A * 6/1998 Wu et al 438/300
5,828,103 A 10/1998 Hsu 257/344
A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide. The remaining silicide typically forms silicided source regions and silicided drain regions that extend over a portion of the adjacent isolation regions such that the silicided source/drain regions are larger than the underlying source/drain regions to provide a larger contact area.
21 Claims, 6 Drawing Sheets
