(io) Patent No.: US 6,275,414 Bl (45) Date of Patent: Aug. 14,2001
(54) UNIFORM BITLINE STRAPPING OF A NONVOLATILE MEMORY CELL
(75) Inventors: Mark W. Randolph; Shane Charles Hollmer, both of San Jose; Pau-Ling Chen, Saratoga; Richard M. Fastow,
Cupertino, all of CA (US)
(73) Assignee: Advanced Micro Devices, Inc.,
Sunnyvale, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/721,035
(22) Filed: Nov. 22, 2000
Related U.S. Application Data
(60) Provisional application No. 60/204,621, filed on May 16, 2000.
(51) Int. CI. G11C 16/04
(52) U.S. CI 365/185.05; 365/63
(58) Field of Search 365/63, 51, 185.05,
An array of memory cells that includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . and each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=l, 2, 3, ... , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and a select transistor is formed every P wordlines, wherein P is greater than N.
17 Claims, 6 Drawing Sheets