(12) United States Patent ao) Patent No.: us 6,228,714 Bi
Choi (45) Date of Patent: May 8,2001
(54) METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE
(75) Inventor: Jung-dal Choi, Suwon (KR)
(73) Assignee: Samsung Electronics Co., Ltd., Suwon (KR)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/387,078
(22) Filed: Aug. 31, 1999
(30) Foreign Application Priority Data
Aug. 31, 1998 (KR) 98-35721
(51) Int. CI.7 H01L 21/8247
(52) U.S. CI 438/258; 438/382; 438/384
(58) Field of Search 438/257-267,
(56) References Cited
U.S. PATENT DOCUMENTS
5,472,892 * 12/1995 Gwen et al. .
5,879,983 * 3/1999 Segawa et al 438/253
5,908,311 * 6/1999 Chi et al 438/258
5,970,338 * 10/1999 Tempel 438/241
6,004,841 * 12/1999 Chang et al 438/238
* cited by examiner
A method for manufacturing a nonvolatile memory device is provided. A first conductive layer is formed on a semiconductor substrate. The first conductive layer is patterned such that an isolated resistor pattern is formed on a predetermined region of a peripheral circuit region. A dielectric layer and a second conductive layer are sequentially formed on the semiconductor substrate. The second conductive layer is patterned to form a second conductive layer pattern exposing the entire dielectric layer of a resistor region in the peripheral circuit region and a predetermined region of the dielectric layer of a MOS transistor region. The second conductive layer pattern, the dielectric layer, and the first conductive layer pattern are sequentially patterned to simultaneously form a gate pattern of a cell transistor and a gate pattern of the MOS transistor. The gate pattern of the MOS transistor includes a predetermined region of the dielectric layer exposed during forming of the second conductive layer pattern. An interdielectric layer is formed on the resultant structure where the gate pattern is formed. The interdielectric layer is patterned to form a contact hole exposing the gate electrode of the MOS transistor and a predetermined region of the resistor pattern.
23 Claims, 7 Drawing Sheets