Semiconductor memory device with test circuit

United States Patent [19]

Arimoto et al.

US0O5185744A

[li] Patent Number: 5,185,744 [45] Date of Patent: Feb. 9, 1993

[73] Assignee:

[21] [22] [30]

[54] SEMICONDUCTOR MEMORY DEVICE WITH TEST CIRCUIT

[75] Inventors: Kazutami Arimoto; Kazuyasu

Fujishima; Yoshio Matsuda; Tsukasa
Ooishi; Masaki Tsukude, all of
Hyogo, Japan

Mitsubishi Denki Kabushiki Kaisha,

Tokyo, Japan

Appl. No.: 479,568
Filed: Feb. 14,1990

Foreign Application Priority Data

Aug. 18, 1989 [JP] Japan 1-213560

[51] Int. CI.5 G11C 29/00

[52] U.S. CI 371/21.2; 371/21.3;

371/21.1

[58] Field of Search 371/21.2, 21.3, 21.1;

365/201

[56] References Cited

U.S. PATENT DOCUMENTS

4.464,750 8/1984 Tatematsu 371/21.2

4.541.090 9/1985 Shiragasawa 371/21.2

4.654.827 3/1987 Childers 365/201

4,654.849 3/1987 White. Jr. et al 371/21

4.670.878 6/1987 Childers 371/21.1

4,744.061 5/1988 Takemae et al 371/21.2 X

4,771.407 9/1988 Takemae et al 365/226

4.841.525 6/1989 Lieske et al 371/21

4.873.669 10/1989 Furutani 365/201 X

4.899.313 2/1990 Kumanoya et al 365/201

5.016.220 5/1991 Yamagata 365/201

5.022.007 6/1991 Arimoto et al 365/201

FOREIGN PATENT DOCUMENTS

0206486 7/1986 European Pat. Off. .
264893 4/1988 European Pat. Off. .

OTHER PUBLICATIONS
Matsumura et al., "On-Chip Parallel Testing Technol-

ogy for VLSI Memories," IEEE Solid-State Circuits Conference, 1985, p. 240.

Inoue et al., "Parallel Testing Technology for VLSI Memories," 1987 International Test Conference, Paper 45.1, pp. 1066-1071.

Shah et al., "A 4Mb DRAM with Cross-point Trench Transistor Cell" IEEE Solid-State Circuits Conference, 1986, pp. 268.

Mano et al., "Circuit Technologies for 16Mb DRAMS," IEEE Solid-State Circuits Conference, 1987.

Kumanoya et al., "A 90ns DRAM with Multi-Bit Test Mode," IEEE Solid-State Circuits Conference, 1985, pp. 240, 241 & 352.

Ohsawa et al., "A 60ns 4Mb CMOS DRAM with Built-in Self-Test," IEEE Solid-State Circuits Conference, 1987, pp. 286, 287 & 430.

Takeshima et al., "A 55ns 16Mb DRAM." IEEE Solid-State Circuits Conference, 1989, pp. 246-247. Arimoto et al., "A 60ns 3.3V 16Mb DRAM," IEEE Solid-State Circuits Conference, 1989, pp. 244-245.

Primary Examiner—Stephen M. Baker

Assistant Examiner—Ly V. Hua

Attorney, Agent, or Firm—Lowe, Price, LeBlanc &

Becker

[57] ABSTRACT

A semiconductor memory device comprises a plurality of memory array blocks (Bl to B4). In each of the plurality of memory array blocks (Bl to B4). a line mode test is performed. Results of the line mode tests performed in the memory array blocks (Bl to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (Bl to B4) to the outside.

40 Claims, 19 Drawing Sheets