(12) United States Patent ao) Patent No.: us 6,412,097 Bi
Kikuchi et al. (45) Date of Patent: Jun. 25,2002
(54) COMPACTING METHOD OF CIRCUIT
LAYOUT BY MOVING COMPONENTS
USING MARGINS AND BUNDLE WIDTHS IN
COMPLIANCE WITH THE DESIGN RULE, A
DEVICE USING THE METHOD AND A
COMPUTER PRODUCT ENABLING
PROCESSOR TO PERFORM THE METHOD
(75) Inventors: Hideo Kikuchi; Keiji Nagano; Yutaka Akimoto, all of Tokyo (JP)
(73) Assignee: NEC Corporation (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/495,804
(22) Filed: Feb. 1, 2000
(30) Foreign Application Priority Data
Feb. 2, 1999 (JP) 11-025310
(51) Int. CI.7 G06F 17/50
(52) U.S. C I 716/2
(58) Field of Search 716/2, 4, 5, 7,
(56) References Cited
U.S. PATENT DOCUMENTS
Two-Dimensional Compaction by "Zone Refining" Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli and Carol H. Sequin/Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA., 23rd Design Automation Conference, 1986 IEEE, Paper 7.3, pp. 115-122.
Kikuchi Hideo "Printed Board Diagonal Wire Compaction Method and Its Evaluation", Joho Shori Gakkai Kenkyu Hoko, (Information Management Society Research Report) (98-DA-88), May 22, 1998, vol. No. 98 Issue No. 43, pp. 29-34.
* cited by examiner
Primary Examiner—Matthew Smith
Assistant Examiner—Thuan Do
(74) Attorney, Agent, or Firm—Hayes Soloway PC.
A layout compaction method adapted to be embodied in computer program product and adapted for compacting a circuit layout having a plurality of layers on which moving objects form layer patterns, wherein the moving objects comprising components and wires. The method assumes a graph problem under condition which prevent the compacted result from violation of the design rule, and then, solves the graph problem to determine a moving order, a moving direction, and a moving distance of each component for moving the components to thereby perform the compacting the circuit layout. After that, the method moves each component according to the moving order, the moving direction and the moving distance to obtain a compacted circuit layout.
79 Claims, 44 Drawing Sheets