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(12) United States Patent ao) Patent No.: us 6,490,193 Bi
van der Wagt et al. (45) Date of Patent: Dec. 3,2002
(54) FORMING AND STORING DATA IN A MEMORY CELL
(75) Inventors: Jan Paul van der Wagt, Newbury Park, CA (US); Gerhard Klimeck,
Glendale, CA (US)
(21) Appl. No.: 09/938,027
(22) Filed: Aug. 22, 2001
(51) Int. CI.7 G11C 11/00
(52) U.S. CI 365/159; 365/175
(58) Field of Search 365/159, 175;
257/25, 17, 22, 28
(56) References Cited
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* cited by examiner
Primary Examiner—-Vu A. Le
(74) Attorney, Agent, or Firm—Baker Botts L.L.P.
FORMING AND STORING DATA IN A
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to digital memory and more particularly to a method and system for generating a memory cell.
BACKGROUND OF THE INVENTION As microprocessors and other electronics applications become faster, storing and accessing data at increasingly high speeds presents more of a challenge. Generally, static random access memories (SRAMs) have been able to operate at higher speeds than dynamic random access memories (DRAMs). In addition, unlike DRAM cells, SRAM cells do not need to be refreshed. This conserves power and makes them continuously available for reading and writing data. However, DRAMs generally are less expensive than SRAMs and are available at densities several times higher than SRAMs. Therefore, conventional memory cells are unable to provide on-chip data storage that includes a combination of high speed, low power, low cost and high density characteristics.
SUMMARY OF THE INVENTION In accordance with the present invention, a method and system for generating a memory cell are provided that substantially eliminate or reduce the disadvantages or problems associated with previously developed systems.
In one embodiment of the present invention, a negative differential resistance device is provided that includes a first barrier, a second barrier and a third barrier. A first quantum well is formed between the first and second barriers. A second quantum well is formed between the second and third barriers.
In another embodiment of the present invention, a memory cell is provided that includes a data storage operable to store a piece of data. The data storage includes a first negative differential resistance device and a second negative differential resistance device. The first and second negative differential resistance devices operate at a low current density. The memory cell includes an access device for accessing the piece of data stored in the data storage.
Technical advantages of the present invention include providing an improved method and system for generating a memory cell. In particular, a double quantum well resonant tunneling diode is included as a part of the memory cell. Accordingly, the low power characteristics of a conventional SRAM cell and the low cost and high density of a conventional DRAM cell are provided together in a new memory cell. In addition, the improved memory cell allows relaxation of transistor leakage requirements. This allows the use of faster, leakier transistors than those normally used in DRAM cells, yielding a higher speed cell.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, descriptions and claims.
BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention and its advantages, reference is now made to the
following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts and wherein:
FIG. 1 is a conduction band diagram of a single quantum well resonant tunneling diode (SRTD);
FIG. 2 is a graph of current as a function of voltage for the SRTD illustrated in FIG. 1;
FIG. 3 is a conduction band diagram of a double quantum 10 well resonant tunneling diode (DRTD) constructed in accordance with the teachings of the present invention;
FIG. 4 is a graph of current as a function of voltage for the DRTD illustrated in FIG. 3; and 15 FIG. 5 is a circuit diagram illustrating a static memory cell constructed in accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE 20 INVENTION
FIG. 1 is a schematic diagram of a single quantum well resonant tunneling diode (SRTD) 10. The SRTD 10 comprises a first barrier 12, a quantum well 14 and a second
25 barrier 16. In operation, an input voltage is applied to the first barrier 12 and an output current flows from the second barrier 16. When a low amplitude voltage is applied to the first barrier 12, almost no electrons tunnel through both the first barrier 12 and the second barrier 16. This results in a
30 negligible output current and the SRTD 10 is switched off. As the voltage increases, the energy of the electrons at the first barrier 12 also increases and the wavelength associated with these electrons decreases. This occurs because an
35 electron's wavelength is determined by dividing Planck's constant by the electron's momentum. When a particular voltage level is reached at the first barrier 12, a specific number of electron wavelengths will fit within the quantum well 14. At this point, resonance is established as electrons
40 that tunnel through the first barrier 12 remain in the quantum well 14, giving those electrons opportunities to tunnel through the second barrier 16. Thus, a current flow is established from the first barrier 12 to the second barrier 16
45 and the SRTD 10 is switched on. However, if the voltage level continues to rise, eventually no electrons will resonate at the proper wavelength to tunnel through the first barrier 12 and the second barrier 16. In this case, the SRTD 10 is switched off. Generally, this property of an SRTD 10 that
50 allows switching back and forth between on and off states as the voltage increases enables biasing of the SRTD 10 for operation in one of three stable states, as illustrated in FIG. 2.
55 FIG. 2 is a graph showing current as a function of voltage for the SRTD 10. The shape of this I-V curve is determined by the quantum effects that are the result of the extreme thinness of the first barrier 12, the quantum well 14 and the second barrier 16, each of which are approximately 10-20
60 atoms thick. As discussed above in connection with FIG. 1, the SRTD 10 may be biased to operate in one of three stable states. These states are the negative-bias valley region 18, the pre-peak region 20, and the positive-bias valley region
SRTDs 10 are generally operated in one of the stable states 18, 20 or 22 and at a high current density. However,