(i9) United States
(12) Patent Application Publication
Okamoto et al.
(54) SEMICONDUCTOR DEVICE AND
MANUFACTURING METHOD OF THE SAME
(76) Inventors: Masahide Okamoto, Yokohama (JP);
Osamu Ikeda, Yokohama (JP); Akira
Muto, Haruna (JP); Yukihiro Satou,
ANTONELLI, TERRY, STOUT & KRAUS,
1300 NORTH SEVENTEENTH STREET
ARLINGTON, VA 22209-3873 (US)
(21) Appl. No.: 11/281,502
(22) Filed: Nov. 18, 2005
(30) Foreign Application Priority Data
Dec. 24, 2004 (JP) 2004-372560
(51) Int. CI.
H01L 29/76 (2006.01)
(52) U.S. CI 257/328
In a semiconductor device having a package structure in which lead terminals connected to electrodes on both of the upper and lower surfaces of a semiconductor chip are exposed from both of the upper and lower surfaces and side surfaces of a sealing body formed of resin, electrodes of the semiconductor chip and the lead terminals are connected by Pb-free connection parts each having a configuration of connection layer/stress buffer layer/connection layer. In each connection part, the connection layer is formed of an intermetallic compound layer having a melting point of 260° C. or higher or Pb-free solder having a melting point of 260° C. or higher, and the stress buffer layer is formed of a metal layer having a melting point of 260° C. or higher and having a function to buffer the thermal stress.