United States Patent [w]
Tran et al.
US005901294A [ii] Patent Number:  Date of Patent:
 METHOD AND SYSTEM FOR BUS
ARBITRATION IN A MULTIPROCESSOR
SYSTEM UTILIZING SIMULTANEOUS
VARIABLE-WIDTH BUS ACCESS
 Inventors: Cang Ngoc Tran; James Allan Kahle,
both of Austin, Tex.
 Assignee: International Business Machines Corporation, Armonk, N.Y.
 Appl. No.: 08/933,155  Filed: Sep. 18, 1997
 Int. CI.6 G06F 13/14
 U.S. CI 395/287
 Field of Search 395/287, 293,
395/728, 729, 857, 200.55
 References Cited
U.S. PATENT DOCUMENTS
4,085,448 4/1978 Kogge 395/287
4,941,086 7/1990 Kiiz 395/294
5,440,698 8/1995 Sindhu et al 395/200.55
5,528,765 6/1996 Milligan 395/287
5,619,726 4/1997 Seconi et al 395/842
Primary Examiner—Gopal C. Ray
Attorney, Agent, or Firm—Anthony V.S. England; Andrew J. Dillon
A method and system for enhanced bus arbitration in a multiprocessor system having multiprocessors coupled to a system memory via a common wide bus. The common wide bus is subdivided into multiple sub-buses which may be accessed individually or in groups by a selected processor, or individual sub-buses may be accessed by multiple processors simultaneously. In response to one or more pending transactions, each processor outputs a request to bus arbitration logic for a number of sub-buses. A maximum number of sub-buses is specified for each processor and the processors are prioritized. Each time a bus request is received from a processor, the number of requested sub-buses is granted, if that number is equal to or less than the specified maximum number of sub-buses for that processor. If the requested number of sub-buses is greater than the specified maximum number of sub-buses for that processor the requested number is granted if no other processor has issued a bus request.
6 Claims, 7 Drawing Sheets