[73] Assignee: General Magic, Inc.. Sunnyvale. Calif.
[21] Appl. No.: 516,840
[22] Filed: Aug. 18, 1995
[30] Foreign Application Priority Data
Jan. 26, 1995 [DE] Germany 195 02 291.2
[51] Int CI.6 G06F 13/40
[52] U.S. CI 395/306; 395/286; 395/200.13
[58] Field of Search 395/280. 182.02.
395/287. 309. 281. 200.2. 200.15. 182.03, 800. 750. 306. 200.13. 286; 340/825.06;
370/85.1. 85.2; 375/257
[56] References Cited
U.S. PATENT DOCUMENTS
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Primary Examiner—Gopal C. Ray
Attorney; Agent, or Firm—Skjerven. Morrill. MacPherson, Franklin & Friel LLP: Forrest E. Gunnison
A low power, single master, variable clock rate, daisychainable. serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.
22 Claims, 30 Drawing Sheets
