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(12) United States Patent
(io) Patent No.: US 6,226,766 Bl (45) Date of Patent: May 1,2001
(54) METHOD AND APPARATUS FOR BUILT-IN SELF-TEST OF SMART MEMORIES
(75) Inventor: Mark G. Harward, Dallas, TX (US)
(73) Assignee: Texas Instruments Incorporated,
Dallas, TX (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 08/224,407
(22) Filed: Apr. 7, 1994
Related U.S. Application Data
(63) Continuation of application No. 07/946,502, filed on Sep. 17, 1992.
(51) Int. C I. G11C 29/00
(52) U.S. CI 714/719; 714/722
(58) Field of Search 371/21.1,21.2,
371/21.5, 67.1, 68.1, 68.2, 29.1; 395/183.18, 182.03, 182.04, 183.16, 183.19, 183.2
(56) References Cited
U.S. PATENT DOCUMENTS
4,715,034 * 12/1987 Jacobson 371/29.1
4,757,503 * 7/1988 Hayes et al 371/21.1
4,899,313 * 2/1990 Kumanoya et al 371/21.1
5,075,892 * 12/1991 Choy 371/21.2
5,109,382 * 4/1992 Fukunaka 371/21.1
5,200,963 * 4/1993 Chau et al 371/68.1
5,231,605 * 7/1993 Lee 371/21.2
5,249,188 * 9/1993 McDonald 371/68.3
5,265,100 * 11/1993 McClure 371/68.1
5,274,648 * 12/1993 Eikiel et al 371/21.2
5,311,520 * 5/1994 Raghavachari 371/21.2
5,400,342 * 3/1995 Matsumura et al 371/21.2
Article by McCluskey, Edward J. entitled "Logic Design Principles" published by Prentice-Hall 1986. pp 458-459, 462-43, 468-471.
* cited by examiner
Primary Examiner—Christine T. Tu
(74) Attorney, Agent, or Firm—Robert L. Troike; Frederick J. Telecky, Jr.
A self-testing smart memory (28) is provided in which memory test circuitry (46) within the smart memory (28) writes a pattern to a data RAM (32) and a broadcast RAM (34) and then reads the data RAM (32) and the broadcast RAM (34) to determine if any failures exist within the memory locations. Furthermore, a data path tester (50) determines the functionality of a data path (30) within smart memory (28).
20 Claims, 2 Drawing Sheets
METHOD AND APPARATUS FOR BUILT-IN
SELF-TEST OF SMART MEMORIES
This application is a Continuation of application Ser. No. 07/946,502, filed Sep. 17, 1992. 5
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic circuits, and more particularly to a method and apparatus for built-in self-test of smart memories. 10
BACKGROUND OF THE INVENTION
Smart memories, or memories which appear externally as standard memory devices yet which contain on-chip processing capabilities, allow for implementation of massive 15 parallel processing systems. As with all electronic circuits, however, the performance of such systems is dependent upon the reliability of each component within the system.
In parallel processing systems using smart memories, each of the smart memories forms an important component 20 of the system that must operate reliably. Therefore, a need has arisen for a built-in self-test scheme for insuring the reliability of each smart memory. Furthermore, this built-in self-test scheme must operate quickly enough so as to not degrade the efficiency of the overall parallel processing 25 system in which the smart memory resides.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a self-testing smart memory is provided which substantially 30 eliminates or reduces disadvantages and problems associated with prior smart memories. In particular, a smart memory is provided which includes a data RAM, a broadcast RAM, and a data path. Memory test circuitry within the smart memory is operable to write a pattern to the data RAM 35 and the broadcast RAM and to compare the contents of the data RAM and the broadcast RAM with the pattern. Any failures in the RAM memory result in an indication that the smart memory failed the self-test. Furthermore, data path test circuitry within the smart memory is operable to test the 40 functionality of the data path.
An important technical advantage of the present invention is the fact that a smart memory using the present invention can internally perform a self-test to determine its operability. Furthermore, this self-test, because it is performed internally, is performed quickly so as to maximize efficiency of a system using smart memories.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:
FIG. 1 is a block diagram of a parallel processing system employing smart memories;
FIG. 2 is a flow chart of a built-in self-test scheme according to the teachings of the present invention;
FIG. 3 is a block diagram of a smart memory including a 60 built-in self-test circuit according to the teachings of the present invention;
FIG. 4 is a block diagram of a built-in self-test circuit according to the teachings of the present invention;
FIG. 5 is a block diagram of a stimulus generator con- 65 structed according to the teachings of the present invention; and
FIG. 6 is a block diagram of a response analyzer constructed according to the teachings of the present invention.
DETAILED DESCRIPTION OF THE
The preferred embodiments of the present invention are illustrated in FIGS. 1 through 6 of the drawings, like numerals being used to refer to like and corresponding parts of the various drawings.
FIG. 1 is a simplified block diagram of a parallel processing system incorporating smart memories. As shown in FIG. 1, CPU 10 is coupled to smart memories 12,14, and 16 through address and data busses. Smart memories 12, 14, and 16 represent n smart memories arrayed to form a massive parallel processing system. Each of these smart memories may be smart memories according to U.S. patent application Ser. No. 07/498,235 filed Mar. 16,1990, entitled "Distributed Processing Memory," and assigned to Texas Instruments Incorporated. That application is herein incorporated by reference.
FIG. 2 illustrates a flow diagram for a built-in self-test for a smart memory according to the present invention. As shown in FIG. 2, the built-in self-test circuitry first senses a test flag at block 18 to initiate the test sequence. The test flag is transmitted by CPU 10 as shown in FIG. 1. Other devices, such as dedicated timers, could also be used to generate the test flag. In a preferred embodiment, the test flag is a pattern transmitted across the address lines to a smart memory. With this embodiment, no extra pins are required to initiate the test sequence. In an alternate embodiment, a dedicated pin could be provided on the smart memory for test initiation. Upon activation of this dedicated test pin, the test sequence would be initiated.
Once the test flag has been sensed at block 18, a result flag is set at block 20. This result flag is set to the "pass" state, indicating that the chip has passed the self-test. If, later in the sequence, it is determined that the smart memory does not pass the self-test, then the result flag will be set to "fail". After the result flag has been set at block 20, the memory locations within the smart memory are tested at decision block 22. The details of this test will be discussed later. If any of the memory locations are not functioning properly, the result flag will be set to "fail" at block 23. If the memory locations are operating properly, then the test sequence continues to decision block 24. At decision block 24, the processing element(s), or data path portion of the smart memory is tested. If the data path is not functioning properly, as will be discussed in detail below, the result flag is set to "fail" at block 23. If the data path is operating properly, then the test flag will be reset at block 26 indicating the end of the test.
In a system incorporating smart memories with built-in self-test circuitry according to the present invention, a CPU or other controller could poll the result flag of each smart memory after completion of the self-test. For example, the CPU could be programmed to begin polling the result flag memory location of each smart memory after a predetermined number of clock cycles. This predetermined number would be equal to the number of clock cycles required for each smart memory to complete its self-test. As an alternate embodiment, each smart memory could send a signal to the host CPU or other controller indicating the results of the self-test. This information could be sent via interrupt signals, or via a dedicated line for indicating test result status after completion of the self-test.
FIG. 3 illustrates a block diagram of a smart memory 28 including a built-in self-test circuit according to the present