[54] LOC SIMM
[75] Inventor: Salman Akram, Boise, Id.
[73] Assignee: Micron Technology, Inc., Boise, Id.
[ * ] Notice: This patent is subject to a terminal disclaimer.
[21] Appl. No.: 09/166,370 [22] Filed: Oct. 5, 1998
Related U.S. Application Data
[60] Continuation of application No. 08/811,935, Mar. 5, 1996, Pat. No. 5,817,535, which is a division of application No. 08/668,765, lun. 25, 1996, Pat. No. 5,723,907.
[51] Int. CI.6 H01L 23/34; H01L 23/02
[52] U.S. CI 257/723; 257/679
[58] Field of Search 257/723, 679
[56] References Cited
U.S. PATENT DOCUMENTS
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5,107,328 4/1992 Kinsman 257/678
5,137,836 8/1992 Lam 437/8
5,162,947 11/1992 Ito 359/692
5,239,198 8/1993 Lin et al 257/693
5,255,156 10/1993 Chang 361/783
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5,418,687 5/1995 Chen 361/761
5,465,470 11/1995 Vongfuangfoo et al 29/559
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5,687,028 11/1997 Ito 359/692
Primary Examiner—-Teresa M. Arroyo
Attorney, Agent, or Firm—Trask, Britt & Rossa
[57] ABSTRACT
A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and case of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a circuit board with an equal number of semiconductor dice attached thereto such that the active surfaces of the dice are exposed through the slots. Wire bonds or TAB connections are made from the exposed active surface of the die, through the slot, and to contacts on the top surface of the circuit board. Dice proven unacceptable during bum-in and electrical testing of the module are replaced by known good dice (KGD) by breaking their respective wire bonds, attaching a KGD to the circuit board, and forming new electrical connections between the KGD and the circuit board.
23 Claims, 5 Drawing Sheets
