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(12) United States Patent
(io) Patent No.: (45) Date of Patent:
US 7,382,199 B2 Jun. 3, 2008
(54) METHODS FOR AUTO-CALIBRATION AND FAST TUNING OF VOLTAGE CONTROLLED OSCILLATORS IN PHASE-LOCK LOOPS
(75) Inventor: Niranjan Talwalkar, New York, NY (US)
(73) Assignee: NanoAmp Solutions, Inc. (KY)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 11/347,114
(22) Filed: Feb. 3, 2006
(65) Prior Publication Data
US 2007/0182494 Al Aug. 9, 2007
(51) Int. CI.
H03L 7/00 (2006.01)
(52) U.S. CI 331/16; 331/44
(58) Field of Classification Search 331/16,
See application file for complete search history. (56) References Cited
U.S. PATENT DOCUMENTS
The present invention provides novel methods for the calibration and fast tuning of VCOs in PLLs. Information for coarse tuning before normal operation are calculated and stored. Therefore, these methods decrease significantly the time needed for a PLL to transition from one frequency to another. These methods include the steps of: determining a digital code Dc to coarse tune to a calibration frequency, Fc; dividing the operating frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band. In tuning to a desired frequency, the following steps are taken: determining the sub-band corresponding to the desired frequency, F, generating the offset for that sub-band, calculating the digital code for coarse tuning the VCO to the desired sub-band, coarse tuning to a frequency within the desired sub-band, and fine tuning to the desired frequency, F.
20 Claims, 1 Drawing Sheet
METHODS FOR AUTO-CALIBRATION AND
FAST TUNING OF VOLTAGE CONTROLLED
OSCILLATORS IN PHASE-LOCK LOOPS
FIELD OF INVENTION 5
The present invention relates to methods for calibrating and fast tuning of voltage controlled oscillators (VCOs) in phase-lock loops (PLLs), and, in particular, it relates to methods for the fast tuning of VCOs in PLLs from one 1° locked frequency to another.
The growing demand for wireless communications has 15 led to designs for radios and other communication equipment that permit the integration of more components onto a single chip. Advances in CMOS semiconductor processing now allow the integration of radio receiver and transmitter onto a single-chip RF transceiver that reduces cost, size, and 20 power consumption. This very high level of integration and the ability to fit a high density of transistors on silicon have enabled new solutions for existing problems.
PLLs using VCOs form the core components for most communication system hardware implementations. Applications with PLLs include radio-frequency (RF) receivers and transmitters for all communication standards, optical fiber communications, network communications, and storage systems applications.
In normal operations, the PLL is expected to step within a specified time from one locked frequency to another, e.g. stepping from a receive channel to a transmit channel in a transceiver. The specified time allowed for this transition in frequency is determined by the specifications of the com- 35 munication system. During such a transition, the PLL must lock and settle to the new frequency and, equally importantly, the PLL must operate optimally at the new frequency within the specified time. Auto-calibrating the VCO allows the PLL to achieve the frequency transition within the 4Q specified time period in spite of the variations introduced during the manufacturing process.
PLLs are generally built with a phase detector, charge pump, filter, VCO, a digital control logic block, D, for programming the VCO, and a divider (+N) such that the 45 frequency of the output signal of the VCO, Fout, is locked to a multiple (N) of a reference frequency Yref. FIG. 1 shows an example of a PLL using a VCO with coarse and fine tuning and FIG. 2 shows a VCO that can be used in a PLL. The coarse tuning is conducted using a switchable capacitor 50 array (8b) that switches in the correct value of capacitance. The fine tuning then uses an analog control voltage signal, ^Tfine-tune^ to set me capacitance of a voltage-dependentcapacitor or varactor, to "capture" the desired frequency. This combination of coarse and fine tuning allows the PLL 55 designer to have a low voltage-to-frequency conversion gain in the VCO (Kvt.0), thereby improving a PLL's performance. In order to minimize Kvco, the value of the varactor is minimized and the values of the coarse tuning capacitors are maximized. Thus, it is essential to switch to the correct value 60 of the coarse tuning capacitor each time a frequency step is requested.
Previously, one method for the fast tuning of a VCO involves the use of a coarse tuning varactor and a fine tuning varactor. The coarse tuning varactor is set based on the 65 output of digital counter and a DAC (digital to analog converter). U.S. Pat. No. 6,566,966. This process is repeated
each time the VCO steps from one frequency to another leading to a slow tuning response.
Another method involves the creation of a look-up table by turning on and off all the possible combinations of the coarse tuning switches and recording and storing the VCO output frequencies for a fixed setting of the fine tuning analog control voltage. U.S. Pat. No. 6,512,419. During normal operation, this table is used to obtain the correct digital code to coarse tune to the desired frequency. The calibration time for this approach is long and a large storage memory is required to store this information.
Another method involves choosing a set of switched varactors during calibration and using the fine tuning varactor to switch from one tuning frequency to another. U.S. Pat. No. 6,933,789. This method has a major drawback in that it cannot ensure a low Kvco. In the application of the method described in this patent, the frequency band of operation determines how small the fine tuning varactor can be and hence how low the Kvco can be. Therefore, previously known methods are not suitable for use in applications requiring high speed PLL frequency transition times.
Due to the limitations of the prior art, it is therefore desirable to have novel methods that provide high speed VCO calibration and fast tuning during frequency transitions.
SUMMARY OF INVENTION
An object of this invention is to provide novel methods for calibrating VCOs in PLLs for applications in high speed tuning such that the time needed for the calibration is short.
Another object of this invention is to provide novel methods for calibrating VCOs in PLLs for applications that require high speed tuning, short calibration time, and limited memory storage.
The present invention provides novel methods for the auto-calibrating and fast tuning of VCOs in PLLs. It calculates and pre-stores information for coarse tuning before normal operation and therefore decreases significantly the time needed for a PLL to transition from one frequency to another. These methods include the following steps: determining the digital code Dc to coarse tune to a calibration frequency, Fc; dividing said frequency band of the PLL into a plurality of sub-bands; determining and storing the information needed to generate the offsets for each sub-band, determining the sub-band of a desired frequency, generating the offset for the sub-band of the desired frequency, calculating the digital code for coarse tuning to the sub-band of the desired sub-band, using the digital code to coarse tuning to the sub-band, and fine tuning to the desired frequency.
An advantage of this invention is that the methods of calibrating VCOs in PLLs of this invention have applications that require high speed tuning, short calibration time, and limited memory storage.
DESCRIPTION OF DRAWINGS
The foregoing and other objects, aspects and advantages of the invention will be better understood from the following detailed description of preferred embodiments of this invention when taken in conjunction with the accompanying drawings in which:
FIG. 1 is a simplified circuit diagram of an example of a PLL using a VCO, where the digital control logic block programs the PLL.
FIG. 2 is a simplified circuit schematic of an example of a VCO with a switchable capacitor array for coarse tuning and varactors for fine tuning.
DETAILED DESCRIPTION OF THE 5
The presently preferred methods of this invention for the fast tuning of PLLs with VCOs within a predetermined frequency band of operation take advantage of the principle io that digital code offsets of sub-bands as they relate to a calibration frequency are independent of variables introduced in the manufacturing process. Presently preferred methods calculates, calibrates, generates and stores information for generating offsets of sub-bands before actual 15 operation and substantially decrease the time needed to tune to a desired frequency. These methods allow PLLs to quickly transition from one frequency to another. The information for generating offsets for each sub-bands are functions of the offsets and the digital code of the reference 20 frequency, Fc. In some embodiments, they can be the actual digital code offsets for the sub-bands. In other preferred embodiments as discussed below, they can be used to calculate the offsets for each sub-band without the use of the digital codes for each of the sub-bands. The size of this 25 information for generating the offsets is relatively small and therefore require small amount of memory for storage.
Presently preferred methods include the following steps: at each pre-chosen time, a calibration routine is used to coarse tune the PLL to a pre-determined calibration fre- 30 quency, Fc. In preferred embodiments, in this initial calibration process, the fine tuning control voltage is fixed at a pre-determined value while the coarse tuning switches of the VCO are thrown to coarse tune to said calibration frequency Fc, i.e., to obtain a center frequency for the VCO as close as 35 possible to Fc. Techniques such as a standard binary search technique may be used to obtain said center frequency. This initial calibration routine generates a digital code, Dc, for said calibration frequency, Fc. This digital code, Dc, is then stored in memory. 40
The frequency band of operation is then subdivided into a pre-determined number of sub-bands. The number of sub-bands determines the maximum variation of the fine tuning control voltage from the pre-determined value across the entire band of operating frequencies. This variation can 45 be minimized by subdividing the entire frequency range into a larger number of bands.
The information for generating the offsets for these subbands can then be calculated and stored. The information is stored because they are relatively independent of process 50 and operating conditions. Each digital code offset, when added to or subtracted from Dc, respectively, yields the digital code for coarse tuning the VCO to a frequency within that particular sub-band, i.e., to coarse tune to the sub-band. In the present discussion, this method of coarse tuning is 55 referred to as coarse tuning to a frequency within a subband.
The choice of Fc determines how the offsets are to be added or subtracted from the digital code Dc. If Fc is the highest frequency of the frequency band, then offset for a 60 sub-band is added to Dc to obtain the digital code for coarse tuning to a frequency within that particular sub-band. If Fc is the lowest frequency of the frequency band, then the offset for a sub-band will be subtracted from Dc to obtain the digital code for coarse tuning to a frequency within that 65 sub-band. If Fc is an intermediate value between the highest and lowest frequency of the frequency band, offsets for a
sub-band will either be added to or subtracted from Dc depending on whether the frequency of the sub-band of interest is lower or higher than Fc.
There are a number of ways to obtain the offset for the sub-bands. In one method, the digital code for a particular frequency within a sub-band can be measured during the calibration process. The offsets for the sub-band can then be defined as either the digital code for that particular frequency subtracting Dc, or Dc subtracting the digital code for that particular frequency, depending on the magnitude of the particular frequency relative to the calibration frequency. For example, if a switchable capacitor array is used to determine the digital code for the coarse tuning, flipping the switches of the capacitors in the switchable capacitor array can provide the offsets for the different frequencies in the sub-bands.
In another method, the offsets can be calculated using standard circuit simulators such as SpectreTM from Cadence Systems. For example, the extracted view of the VCO can be simulated to obtain the code Dhigh for coarse tuning to the highest frequency in the band. Thus, Dhigh is the digital code which, when inputted to the VCO, causes it to oscillate very close to the highest frequency of the band. The search for Dhigh can be performed using an algorithm such as binary search. The other input to the VCO, V'ctrl, is set at a pre-determined fixed voltage. In an identical fashion, Dw, the digital code for coarse tuning to the lowest frequency in the band can be obtained. The other input to the VCO, Vcft7, is again set at the same pre-determined fixed voltage as during the search for Dhigh. The total offset for the band, Otot, is Dw, minus Dhigh since Dw is greater than Dhigh. This total offset is one type of the information that can be used for generating the offsets for each sub-band. It is a fixed number that can be stored in the digital memory.
Of course, the total offset does not necessarily have to be defined as the difference between the digital codes for coarse tuning to the highest and lowest frequencies. A different total offset Otot can be defined and calculated as the difference in the digital codes for coarse tuning to any two frequencies, Yx and F2, within said frequency band of operation.
If silicon measurements on a test run of a prototype show that the offset is not exactly as simulated, a more accurate offset can be obtained from measurements in an identical fashion to that described above. The corrected offset would then be hard-wired in the digital memory before mass production.
The offset for each for each of the sub-bands can then be calculated by interpolating or extrapolating the total offset, Otot over the frequency band. For example, when the Fc is the highest frequency of the band and Otot is defined as the difference between the digital codes of the highest and lowest frequency within the pre-determined frequency band, the offset for each sub-band can be calculated by interpolating the total offset Otot. The offset for the highest sub-band at the highest frequencies can equal zero and the offset for the lowest sub-band at the lowest frequencies can equal Otot. The above described steps can be performed during normal operation or just once before the normal operation and stored in memory.
Variations of the above-described methods for determining the total offset can be used to obtain the offset for each sub-band. For example, the offset between two frequencies in the frequency band, not necessarily the highest and lowest, can be found in a similar manner. The offsets for the each sub-band can then be obtained by interpolating and/or extrapolating this new offset found over the frequencies of the entire band.