WORD LINE CONTROL CIRCUIT
 Inventor: Toru Ishikawa, Tokyo, Japan  Assignee: NEC Corporation, Tokyo, Japan
 Appl. No.: 09/301,861
 Filed: Apr. 29, 1999
 Foreign Application Priority Data
Apr. 30, 1998 [JP] Japan 10-120525
 Int. C I. G11C 8/00
 U.S. CI 365/230.06; 365/230.03;
 Field of Search 365/230.06, 230.03,
 References Cited
U.S. PATENT DOCUMENTS
5,848,006 12/1998 Nagata 365/230.06
5,910,927 6/1999 Hamamoto et al 365/230.03
5,970,016 10/1999 Ohsawa 365/230.03
FOREIGN PATENT DOCUMENTS
409198900 7/1997 Japan . 9-231755 9/1997 Japan .
"Advanced Electronics 1-9," Super LSI Memory, Baifukan, First Edition Published Nov. 5, 1994, Japan.
According to one embodiment, a word line control circuit (100) includes certain sub-array word lines (SWL-00 to SWL-03) coupled to one bank (BANKO)ol memory cells and other sub-array word lines (SWL-10 to SWL-13) coupled to another bank (BANK1) ol memory cells. Complementary main word lines (MWL and /MWL) are provided that can select groups of sub-array word lines in both banks when activated. Latch circuits (104-AO to 104Bl) are provided for latching main word lines values. Such an arrangement allows a complementary main word line values to be latched for a first bank (BANK0), thereby selecting a group of sub-array word lines (SWL-00 to SWL-03) in the first bank (BANK0). The complementary main word line (MWL and /MWL) can then be activated again. The second complementary main word line values can then latched for a second bank (BANK1), thereby selecting a group of sub-array word lines (SWL-10 to SWL-13) in the second bank (BANK0). Such an arrangement allows a main word line to be common to both banks, while still allowing individual selection of different subarray word lines in different banks.
20 Claims, 7 Drawing Sheets