METHOD FOR PRODUCING A
SEMICONDUCTOR COMPONENT WITH
ELECTRICAL CONNECTION TERMINALS
FOR HIGH INTEGRATION DENSITY
SUMMARY OF THE INVENTION
The present invention relates to semiconductor components having a special structure for electrical connection which allows a high integration density of functional elements on a chip.
For complex CMOS circuits, a positive supply voltage and a negative supply voltage (VDD and VSS) must be fed in, and a multiplicity of signal lines must be routed between the individual transistors. For this purpose, a plurality of wiring planes, i.e. layer-type portions having interconnections and metallizations, must be used, which contain, for example, aluminum interconnections which are insulated from one another by a dielectric such as. for example. Si02. Connections between these individual planes of interconnections and contacts or from the bottom plane to the transistors and other functional elements on the chip are produced by metal contacts. These contacts are essentially metal-filled holes in the dielectric. With increasing circuit complexity, an ever-increasing number of independent planes with interconnections is necessary in order to provide the requisite electrical connections in sufficient density. As the number of planes increases, the requirement forplanarity of the respective dielectric intermediate layers increases, since if the individual layers are insufficiently planarized. production of the next interconnection plane gives rise to technological difficulties. The minimum achievable dimensions of the individual structures consequently increase drastically toward the upper planes. The so-called packing density that can be achieved is thereby considerably reduced. Small capacitances between the signal lines are furthermore necessary for high operating speeds. Supply lines to the external electrical connection terminal should have the lowest possible input line resistances and a high current-carrying capacity. In this case, high capacitances are more beneficial, since these capacitances act as charge stores and can block current spikes.
BACKGROUND OF THE INVENTION
The object of the present invention is to specify a design for a semiconductor component, in which the complexity of the electrical connections is reduced for large-scale integration of the functional elements.
In general terms the present invention is a method for producing a semiconductor component having at least one buried full-area metal layer which is provided with a connection terminal for external power supply, and having active functional elements in a silicon layer. In a first step, a layer structure consisting of each buried full-area metal area and this silicon layer for these active functional elements is produced on a substrate. Dielectric layers for electrical insulation are in each case applied between these layers. In a second step, these active functional elements are produced. In a third step, openings which in each case extend such that a region, intended for making contact, of a functional element is exposed in each opening. In a fourth step, a dielectric is applied onto the wall of these openings up to a height provided for electrical insulation. This region provided for making contact remains exposed in each case. In a fifth step, these openings are filled with metal in order to produce vertical electrically conductive connections between the respective metal layer and this region, provided for making contact, of the functional element.
Advantageous developments of the present invention are as follows.
The fourth step is carried out by depositing the dielectric into the openings, etching away the dielectric anisotropically
5 outside and on the bottom of the openings, filling the openings with a material that resists the etching, in each case up to the height up to which the dielectric is intended to remain, removing the portion of dielectric thereby remaining exposed and removing the material that resists this etching.
10 In the first step, each buried full-area metal layer is produced from a silicide of a metal from the group titanium, tungsten and tantalum. The first step is carried out by. in a first additional step.
15 aPPlyin8 at least one full-area metal layer onto a first substrate and covering it with a full-area dielectric layer and applying a dielectric layer over the whole area onto a second silicon substrate. In a second additional step, these dielectric layers are brought to face each other and are connected
20 together by wafer bonding.
The semiconductor component is produced in the framework of a CMOS process. In the first step, two such metal layers are produced, which are each provided with a connection terminal for the positive pole or the negative pole.
25 respectively, of a supply voltage.
The semiconductor component according to the invention reduces the complexity of the electrical connections by virtue of the fact that full-area metal layers are present for input of the external supply voltage. These metal layers are
30 buried in the substrate or between the substrate and the active semiconductor layers and are insulated from one another by dielectric intermediate layers. The semiconductor component according to the invention can be produced particularly advantageously with CMOS circuits using SOI
35 (silicon on insulator) technology. The signal lines are in mis case arranged conventionally over the functional elements, i.e. on the side remote from the substrate. The signal lines are produced in the form of conventional interconnections and metal contacts. It is possible for only one full-area
40 buried metal layer, for example as the ground connection contact, or at least two metal layers, each for one of the supply voltages VDD and VSS, to be present. Connection of the functional elements (transistors and the like) to these metal layers is produced by vertical conductive connections
45 through the dielectric intermediate layers. These connections are, for example, thin vertically arranged metal pins or metal cylinders which are laterally enclosed all round by the dielectric of the intermediate layers. Instead of this, it is also possible for larger apertures to be etched in the layer planes
50 and for the vertical connections to be produced by interconnections which do not completely fill these openings. However, in view of the desired planar design of the semiconductor component, a buried form of contact between metal layers and interconnections, which are respectively
55 arranged in one plane of the layer structure, is expedient. When a plurality of full-area metal planes for the supply voltage are present, the connection terminals of the active functional elements in the layer structure are connected to the full-area metal planes arranged further away using
go vertically arranged conductors which are routed through apertures in the full-area metal planes arranged in between and are insulated from the latter by dielectric sheathing.
This semiconductor component design according to the invention has the advantage that a complete metal layer is in
65 each case used for feeding in each pole of a supply voltage. Microstructuring is therefore not required for this input line. The production outlay is thereby reduced and leads to a