Generation of sub-netlists for use in incremental compilation

(54) GENERATION OF SUB-NETLISTS FOR USE IN INCREMENTAL COMPILATION

(75) Inventors: Bruce Pedersen, San Jose, CA (US);

Francis B. Heile, Santa Clara, CA
(US); Marwan Adel Khalaf, Santa
Clara, CA (US); David Wolk Mendel,

Sunnyvale, CA (US)

(73) Assignee: Altera Corporation, San Jose, CA (US)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 247 days.

This patent is subject to a terminal disclaimer.

(21) Appl. No.: 09/639,657

(22) Filed: Aug. 15, 2000

Related U.S. Application Data

(63) Continuation of application No. 08/958,002, filed on Oct.

27, 1997, now Pat. No. 6,134,705. (60) Provisional application No. 60/029,277, filed on Oct. 28,

1996.

(51) Int. CI.7 G06F 17/50

(52) U.S. CI 716/18; 716/2; 716/3

(58) Field of Search 716/1, 2, 3, 6,

716/11, 12, 18

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Primary Examiner—-Vuthe Siek

Assistant Examiner—Leigh Marie Garbowski

(74) Attorney, Agent, or Firm—Beyer Weaver & Thomas,

LLP

(57) ABSTRACT

A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a "sub-netlist" within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.

28 Claims, 18 Drawing Sheets

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