(12) United States Patent ao) Patent No.: Us 7,432,188 B2
Tsai et al. (45) Date of Patent: Oct. 7,2008
(54) STRUCTURE OF BUMPS FORMING ON AN UNDER METALLURGY LAYER AND METHOD FOR MAKING THE SAME
(75) Inventors: Chi-Long Tsai, Kaohsiung (TW);
Wan-Huei Lu, Kaohsiung (TW)
(73) Assignee: Advanced Semiconductor
Engineering, Inc., Kaohsiung (TW)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl.No.: 11/601,684
(22) Filed: Nov. 20, 2006
(65) Prior Publication Data
US 2007/0117368 Al May 24, 2007
(30) Foreign Application Priority Data
Nov. 21,2005 (TW) 94140860 A
(51) Int. CI.
H01L 21/44 (2006.01)
(52) U.S. CI 438/614; 257/738
(58) Field of Classification Search 438/612 614;
257/E21.508 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
3,821,785 A * 6/1974 Roseetal 257/751
A structure of bumps formed on an under bump metallurgy layer (UBM layer) and a method for making the same, wherein the structure includes a wafer, a UBM layer, a second photo resist and a bump. The wafer has a plurality of solder pads and a protection layer, and the protection layer covers the surface of the wafer and exposes parts of the solder pads. The UBM layer is disposed on the solder pads and the protection layers, and has an undercut structure. The second photo resist is disposed in the undercut structure. The bump is disposed on the UMB layer, so that the UMB layer will not react with the bump during a reflow process and the problem of stress concentration will be avoided so as to make the bump more stable.
9 Claims, 7 Drawing Sheets