US 7,482,630 B2 Jan. 27, 2009
(54) NAND MEMORY ARRAYS
(75) Inventor: Roger W Lindsay, Boise, ID (US)
(73) Assignee: Micron Technology, Inc., Boise, ID (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 248 days.
(21) Appl.No.: 11/209,301
(22) Filed: Aug. 23, 2005
(65) Prior Publication Data
US 2005/0281092 Al Dec. 22, 2005
Related U.S. Application Data
(62) Division of application No. 10/692,430, filed on Oct. 23, 2003, now Pat. No. 7,419,895.
A NAND memory array has a substrate, a source select gate formed on the substrate, and a drain select gate formed on the substrate. A string of floating-gate memory cells is formed on the substrate and is connected in series between the source select gate and the drain select gate. A drain contact has a head connected substantially perpendicularly to a stem. The head is aligned with the drain select gate and overlies a dielectric layer formed on the drain select gate. The stem overlies a polysilicon plug formed on the substrate. A bit line contact is in direct electrical contact with the head.
30 Claims, 7 Drawing Sheets