United States Patent   Patent Number: 4,628,480
Floyd  Date of Patent: Dec. 9, 1986
 ARRANGEMENT FOR OPTIMIZED UTILIZATION OF I/O PINS
 Inventor: William M. Floyd, Livonia, Mich.
 Assignee: United Technologies Automotive, Inc., Dearborn, Mich.
 Appl. No.: 540,573
 Filed: Oct. 7,1983
 Int. Q." G06F 1/00
 U.S. a 364/900; 365/233
 Field of Search ... 364/200 MS File, 900 MS File;
 References Cited
U.S. PATENT DOCUMENTS
4,130,900 12/1978 Watanabe 365/230
4,397,001 8/1983 Takemae 365/193
4,434,474 2/1984 Best et al 364/900
4,484,329 11/1984 Slamka et al 371/25
4,495,603 1/1985 Varshney 365/233
FOREIGN PATENT DOCUMENTS
0009862 7/1979 European Pat. Off. . 58-139226 6/1983 Japan .
Article entitled "Serial Network Simplifies the Design of Multiple Microcomputer Systems", by Don Folkes, 8079 Electro/81 Conference Record, vol. 6, (1981) Apr. 7-9, New York, NY.
Primary Examiner—James D. Thomas
Assistant Examiner—Thomas C. Lee
Attorney, Agent, or Firm—Stephen A. Schneeberger
Arrangement for the input of address data to an integrated circuit (IC) via the same input/output (I/O) terminal pins utilized for the transfer of data is disclosed. The I/O data pins each have an output data latch and an address latch connected to the respective pin and positioned internally of the circuit's interface. A logic level is applied to each of those I/O data pins via a respective external resistor for normally biasing the pin to that logic level. A further I/O pin at the circuit's interface is connected to a common conductor positioned externally of the interface. Diodes are connected between selected ones of the I/O data pins and the common conductor in accordance with a desired address. A level controller responds to a power-on-reset (POR) gating signal to switch the common conductor between a high impedance state and a logic level which effects conduction by the diodes, to enter address data bits. Address latches in the IC store the entered address data bits. The end of the gating signal enters the address bits into their respective latches. Output of data to the I/O data pins is via respective tri-stated transmit devices having their inputs connected to the outputs of respective data latches, and serves to extend that data value or its inverse to a respective I/O pin when enabled upon cessation of the POR signal.
9 Claims, 14 Drawing Figures