MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
Inventors: Ming-Huei Shieh, Cupertino, CA (US); Kazuhiro Kurihara, Tokyo (JP)
Assignee: Spansion LLC, Sunnyvale, CA (US)
Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
Filed: Jan. 22, 2008
Prior Publication Data
US 2008/0117678 Al May 22, 2008
Related U.S. Application Data
Continuation of application No. 10/600,065, filed on Jun. 20, 2003, now Pat. No. 7,324,374.
U.S. CI 365/185.03; 365/185.01;
Field of Classification Search 365/185.03,
365/185.01, 185.05, 185.07, 185.2, 185.33, 365/185.21, 185.09, 185.25 See application file for complete search history.
U.S. PATENT DOCUMENTS
A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408,410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).
13 Claims, 12 Drawing Sheets