United States Patent m
Green et al.
[54] METHOD AND APPARATUS FOR VALIDATING I/O ADDRESSES IN A FAULT-TOLERANT COMPUTER SYSTEM
[75] Inventors: Gregory M. Green, Boxborough;
Steven Kohalmi, Newton; Karen R.
Bricknell, Berlin, all of Mass.
[73] Assignee: Stratus Computer, Marlboro, Mass.
[21] Appl. No.: 356,561
[22] Filed: Dec. 15,1994
[51] Int. CI.6 G06F 11/00
[52] U.S. CI 395/185.06; 395/421.11;
395/411; 395/413
[58] Field of Search 395/185.06, 185.07,
395/185.05, 406, 410, 411, 412, 413, 416, 421.08, 421.11; 371/51.1
[56] References Cited
U.S. PATENT DOCUMENTS
3,192,362 6/1965 Cheney 395/185.05
4,637,024 1/1987 Dizon et al 371/185.06
4,677,546 6/1987 Freeman et al 364/200
4,774,659 9/1988 Smith et al 364/200
4,777,575 10/1988 Streckeretal 364/200
4,942,519 7/1990 Nakayama 364/200
5,115,490 5/1992 Konuro et al 395/400
5,276,823 1/1994 Cuts, Jr. et al 395/575
ii i Iii ii it 11 ii 11; Iiiii ii i if inn nun n in iii;
US005586253A
[ii] Patent Number: 5,586,253 [45] Date of Patent: Dec. 17,1996
5,321,706 6/1994 Holm et al 371/51.1
5,357,615 10/1994 Peek et al 395/275
5,371,868 12/1994 Koning et al 395/400
5,392,302 2/1995 Kemp et al 371/51.1
5,404,361 4/1995 Casorso et al 395/185.05
5,426,747 6/1995 Weinreb et al 395/400
5,440,710 8/1995 Richter et al 395/417
5,449,849 10/1995 Bergkvist, Jr. et al 395/403
5,463,755 10/1995 Dumarot et al 395/425
Primary Examiner—Robert W. Beausoliel, Jr.
Assistant Examiner—Joseph E. Palys
Attorney, Agent, or Firm—Cesari and McKenna
[57] ABSTRACT
A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.
2 Claims, 15 Drawing Sheets
