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United States Patent [w]
Horn et al.
US006079040A [ii] Patent Number:  Date of Patent:
 MODULE LEVEL SCAN TESTING
 Inventors: Pat Y. Horn, Milpitas; T. Dean Skelton, San Jose, both of Calif.
 Assignee: Chips & Technologies, Inc., San Jose, Calif.
 Appl. No.: 08/711,114  Filed: Sep. 9, 1996
 Int. CI. G06F 11/00
 U.S. CI 714/738
 Field of Search 371/27.1, 22.31,
371/22.32, 22.34, 22.1, 27.5; 395/183.06
 References Cited
U.S. PATENT DOCUMENTS
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4,241,307 12/1980 Hong 324/73 R
4,745,355 5/1988 Eichelberger et al 324/73 R
4,799,164 1/1989 Hellekson et al 235/467
4,854,039 8/1989 Wendt 29/832
4,897,838 1/1990 Tateishi 372/22.3
5,042,034 8/1991 Correale, Ir. et al 371/22.3
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5,448,575 9/1995 Hashizume 371/22.3
5,459,735 10/1995 Narimatsu 371/22.3
5,477,167 12/1995 Chua 326/41
Williams, Thomas W., et al., "Design for Testability—A Survey", Proceedings of the IEEE, vol., 71, No. 1, Jan. 1983, pp. 98-112.
Primary Examiner—-Vincent P. Canney
Attorney, Agent, or Firm—D'Alessandro & Ritchie
A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.
13 Claims, 2 Drawing Sheets
MODULE LEVEL SCAN TESTING
BACKGROUND OF THE INVENTION
The present invention relates to the testing of integrated circuitry and, more particularly, to the scan testing of inte- 5 grated circuitry grouped in modules capable of being used in other integrated circuitry.
The integrated circuitry on a chip is commonly tested. This testing may be associated with design analysis. Moreover, production chips of an integrated circuit design 10 are checked for manufacturing flaws before being furnished to a customer.
The above checking includes applying a test program to the circuitry to determine if logic on the chip will react as desired to various electrical inputs.
The test program may include one or more scan patterns to be applied to the specimen of the circuit to be tested. Scan patterns can typically detect more manufacturing flaws than manually generated test patterns. Scan patterns are usable 2Q only on circuits which include particular logic for scanning. These special circuits are called "scanned circuits". In a scanned circuit, some or all of the flip-flops are replaced with scan flip-flops. Additional scan support logic may also be present. A scan flip-flop typically has two modes: a 2J normal operation mode, and a scan test mode. The scan flip-flops and the scan support logic provide an additional method of controlling and observing the circuits' internal values.
A scan pattern includes one or more test sequences which, 30 in turn, include one or more "scan operations". A scan operation is a set of input stimulus which loads specified values into the scan flip-flops (a scan-in operation), or extracts expected values from the scan flip-flops (a scan-out operation). Note that scan-in and scan-out operations can 35 occur simultaneously. During a scan operation, the scan flip-flops are placed into scan test mode, values are loaded and/or extracted from the scan flip-flops, then the scan flip-flops are placed back into normal operation mode. A typical test sequence in a scan pattern consists of a scan-in 40 operation, a set of input stimulus (with the scan flip-flops in normal operation mode), and a scan-out operation.
Each of the scan patterns making up a test program is formed by applying an ATPG (Automated Test Pattern Generation) program and tools to an integrated circuit 45 design having scan flip-flops to develop ATPG patterns. The ATPG program takes advantage of the presence of the scan flip-flops by loading desired values into the scan flip-flops or by specifying expected values that should be extracted from such scan flip-flops. Atranslator program converts the ATPG 50 pattern into a scan pattern designed for the circuitry to be tested.
In the basic implementation of scan, a design is tested as one entity, and the design's scan flip-flops are interconnected into a single, long shift register (a scan chain). Values are 55 loaded and/or extracted from the scan flip-flops by serially shifting in/out one bit per clock cycle. (Loading a scan chain of 800 scan flip-flops requires 800 clock cycles.) Because such serial scan testing is relatively time consuming, many of those in the art have divided a design's scan flip-flops into 60 numerous scan chains. Loading eight scan chains of 100 scan flip-flops each, requires 100 clock cycles as opposed to 800 clock cycles. The ATPG program is still run on the entire design; the resulting ATPG patterns are translated to support multiple scan chains. In other words, the scan patterns in 65 both of the above scenarios, the more efficient approach just described and the basic approach, are generated on a chip
level basis. That is, the original ATPG pattern and its tools are applied to the full piece of integrated circuitry rather than to selected parts of the same.
New ATPG patterns are required whenever the logic changes, especially if scan flip-flops are added and deleted from the design. Moreover, generating compact, high coverage ATPG patterns often requires multiple runs with different tool constraints and options. The scan patterns developed from an ATPG arrangement also must be debugged. This debugging typically is a long process because of (not infrequent) mismatches between the circuit design's behavior and the ATPG tools zero-delay simulations.
SUMMARY OF THE INVENTION
The present invention provides for the development and use of ATPG patterns for those individual parts of a specimen of circuitry design that find use in other circuitry designs. As the logic is reused in different circuit designs, the ATPG patterns for such logic can also be reused.
From the broad standpoint the invention includes several steps for the development of input stimulus values for performing scan operations on a design of logic circuitry. The first step is separating from the design a discrete logic module usable in other designs of logic circuitry. If the design to be tested has more than one module which is so usable in other circuitry, the design is divided into multiple modules. The method includes thereafter applying an ATPG program and its tools to the module while not applying the same to the remainder of the circuitry. Again, if the design has more than one module of logic usable separately in other logic designs, the ATPG program and its tools is applied separately to each of the modules while not being applied to the others.
Specific scan patterns for the reusable modules of the circuitry are then prepared from the reusable ATPG patterns. (Note that unlike the scan patterns, the ATPG patterns are not dependent on the specific circuitry within which the particular reusable module is incorporated.) As mentioned previously, it is common for a test program to include a multiple number of test sequences and, hence, scan operations. From the broad standpoint each test sequence includes loading components of a module under test with predetermined values (a scan-in operation), applying input stimulus values to the module, and thereafter evaluating the response (a scan-out operation). The step of applying includes, most desirably, replacing with controlled inputs, the input to the selected module which otherwise would be provided by other aspects of the integrated circuitry, with known inputs.
The invention includes not only methods as described above, but also apparatus for performing the same.
Other features and advantages of the invention either will become apparent or will be described in connection with the following, more detailed description of a preferred embodiment of the invention and variations.
BRIEF DESCRIPTION OF THE DRAWING With reference to the accompanying drawing: FIG. 1 is a schematic diagram of a prior art arrangement; FIG. 2 is a schematic diagram of a preferred embodiment
of the invention; and
FIG. 3 is a more detailed schematic diagram portion of the
preferred embodiment of FIG. 2.
DETAILED DESCRIPTION OF THE
The following relatively detailed description is provided to satisfy the patent statutes. It will be appreciated by those