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United States Patent [w]
Canella et al.
 PROCESS FOR TESTING A SEMICONDUCTOR DEVICE
 Inventors: Robert L. Canella, Meridian; Warren M. Farnworth, Nampa, both of Id.
 Assignee: Micron Electronics, Inc., Nampa, Id.
 Appl. No.: 08/893,007  Filed: Jul. 15, 1997
Related U.S. Application Data
 Division of application No. 08/636,449, Apr. 23, 1996, Pat. No. 5,648,728, which is a continuation of application No. 08/205,678, Mar. 1, 1994, Pat. No. 5,510,723.
 Int. C I. C01R 31/02
 U.S. CI 73/865.8
 Field of Search 73/865.8; 324/754,
324/758, 761, 762, 765; 269/21, 55-58, 289 R; 248/346.01, 362; 348/87, 94, 95
 References Cited
U.S. PATENT DOCUMENTS
3,863,764 2/1975 Myslinski et al 209/111.8
4,410,168 10/1983 Gotman .
Primary Examiner—Robert Raevis
Attorney, Agent, or Firm—Trop, Primer & Hu, PC.
A method for positioning a workpiece comprises the steps of providing a pedestal having a chamfered portion and a generally circular portion having a first diameter and providing a table having a hole therein and a chamfered portion, the hole having a second diameter larger than the first diameter. The inventive method further includes the steps of supporting the pedestal with the table, the chamfered portion of the table contacting the chamfered portion of the pedestal and placing the workpiece on the pedestal. Next, the chamfered portion of the pedestal is urged away from the table. Subsequent to the step of urging the chamfered portion of the pedestal away from the table, the pedestal is moved in at least one of X-, Y-, and theta directions while the generally circular portion of the pedestal extends into the hole in the table.
18 Claims, 2 Drawing Sheets
PROCESS FOR TESTING A
This is a division of application Ser. No. 08/636,449 filed Apr. 23, 1996 and issued Jul. 15, 1997 as U.S. Pat. No. 5 5,648,728, which is a continuation of application Ser. No. 08/205,678 filed Mar. 1, 1994, issued Apr. 23, 1996 as U.S. Pat. No. 5,510,723.
FIELD OF THE INVENTION 10
This invention relates to the field of semiconductor device manufacturing. More specifically, an apparatus for transporting and testing an unpackaged semiconductor device is described.
BACKGROUND OF THE INVENTION
Many types of semiconductor devices are made using similar manufacturing procedures. A starting substrate, usually a thin wafer of silicon, is doped, masked, and etched 2Q through several process steps, the steps depending on the type of devices being manufactured. This process yields a number of semiconductor devices (dies) on each wafer produced. Each die on the wafer is given a brief test for functionality, and the nonfunctional devices are mechani- ^ cally marked or mapped in software. This probe test is only a gross measure of functionality, and does not insure that a device is completely functional or has specifications that would warrant its assembly in a package.
If the wafer has a yield of grossly functional devices 30 which indicates that a significant number of devices from the wafer are likely to be fully operative, the devices are separated with a die saw (diced) into discrete devices, and the nonfunctional devices are scrapped while the functioning devices are individually encapsulated in plastic packages or 35 mounted in ceramic packages with one device in each package. After the diced devices are packaged they are rigorously electrically tested. Components which become nonfunctional or which operate below full industry specifications are scrapped or devoted to special uses. 40
Packaging unusable devices only to scrap them after testing is costly. Given the relatively low profit margins of commodity semiconductor components such as dynamic random access memories (DRAMs) and static random access memories (SRAMs), this practice is uneconomical. 45 However, no thorough, cost effective, and automated method of testing an unpackaged device is available which would prevent this unnecessary packaging of nonfunctional and marginally functional devices.
It is becoming more common to package multiple inte- 50 grated circuit devices as a single unit, known as a multi chip module (MCM). Testing of each device before it is assembled into the MCM is difficult because the conventional lead frame package is not typically used for the manufacture of MCMs. The reliability of the entire package 55 is compromised by the individual component with the least performance capability. Although there is no industry standard by which devices are tested and considered "known good die," it is desirable to have the ability to retest the individual die being used on a particular MCM to increase 60 the potential for greater yields. The ability to presort an individual device is limited to results obtained through probe testing, which is only a gross measure of functionality and does not typically result in information regarding access times or reliability. An MCM is burned in after assembly, 65 which can result in the failure of one or more DRAMs. If a single device is nonfunctional or operates outside of accept
able specifications, the entire component fails and all devices in the package are scrapped or an attempt is made to "re-work" the MCM. There is presently no cost-effective way to reclaim the functioning devices.
Statistically, the yields of MCMs decrease in proportion to the increasing number of devices in each module. The highest density modules have the lowest yields due to their increased total silicon surface area. Testing of unpackaged devices before packaging would be desirable as it would result in reduced material waste, increased profits, and increased throughput. Using only known good devices in multichip modules would increase yields significantly. An apparatus which allows for the handling and testing of an unpackaged semiconductor device would be desirable. Similarly, an apparatus which would allow a user of diced devices purchased from a manufacturer to test incoming devices would be desirable.
SUMMARY OF THE INVENTION
An automated apparatus for testing an unencapsulated diced semiconductor device comprises a test head. The test head comprises a carousel table having a top and a bottom. A carousel table portion (which can be the carousel table itself or an insert in the carousel table) has a chamfered portion. The test head further comprises a chamfered pedestal received by the chamfered portion of the carousel table. The pedestal has a bottom portion which extends through the carousel table below the carousel table bottom. The semiconductor device to be tested is received by the pedestal.
The test head also has a chuck for receiving the bottom portion of the pedestal. The chuck is moveable in four directions, the X, Y, Z, and theta directions. A probe is positioned above the pedestal for the passage of an electric signal to the semiconductor device. The apparatus further comprises a camera for detecting a position of said probe relative to a position of the semiconductor device.
In operation, the chuck receives the bottom portion of the pedestal and urges the pedestal from the chamfered portion of the carousel table toward the probes. The chuck moves in the X, Y, and theta directions responsive to a signal from the camera to align the semiconductor device with the probes. The probes then make contact with the diced semiconductor device on the pedestal.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view of one embodiment of the invention; and
FIG. 2 is a cross-section showing a test head assembly of FIG. 1.
It should be emphasized that the drawings herein are not to scale but are merely schematic representations and are not intended to portray the specific parameters or the structural details of the invention, which can be determined by one of skill in the art by examination of the information herein.
DETAILED DESCRIPTION OF THE
FIG. 1 is a plan view of one embodiment of the invention. The flow of a diced device though the assembly as shown in FIG. 1 is generally from left to right.
Prior to testing the device with the inventive assembly, a semiconductor wafer 10 is produced according to means