« PreviousContinue »
United States Patent m
[ii] Patent Number: 4,613,852  Date of Patent: Sep. 23, 1986
 DISPLAY APPARATUS
 Inventor: Kinya Maruko, Oume, Japan
 Assignee: Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, Japan
 Appl. No.: 546,041
 Filed: Oct. 27, 1983
 Foreign Application Priority Data
Oct. 29, 1982 [JP] Japan 57-190309
 Int. a." G09G 1/14
 U.S. a 340/703; 340/723;
 Field of Search 340/703, 723, 747, 798,
 References Cited
U.S. PATENT DOCUMENTS
4,149,184 4/1979 Giddings et al 340/703
4,183,046 1/1980 Dalke et al 340/703
4,303,986 12/1981 Lans 340/703
4,509,043 4/1985 Mossaides 340/703
O'Brien et al., "Videotex Presentation Level Procotol: Augmented Picture Description Instructions" (Feb. 1982).
PD7220 GDC User's Manual; Nippon Electric Co., Ltd. (Mar. 1982).
Primary Examiner—Gerald L. Brigance
Attorney, Agent, or Firm—Schwartz, Jeffery, Schwaab,
Mack, Blumenthal & Evans
In a display apparatus comprising a plurality of memory planes, and a graphic display controller for writing data in and reading data from the memory planes, a logical operation circuit capable of performing logical operation in a plurality of different modes of operation is provided and is controlled to perform, in the mode latched in a mode registration circuit, logical operation on the data read from the memory planes. A selector selectively outputs data from one of the memory planes or data from the logical operation circuit.
5 Claims, 4 Drawing Figures
U.S. Patent Sep. 23,1986 Sheet 1 of2 4,613,852
Fl G. I
U.S. Patent Sep.23,1986 Sheet2of2 4,613,852
F I G. 2
BACKGROUND OF THE INVENTION
This invention relates to an improvement of a display 5 apparatus.
With the increase in capacity and decrease in costs of IC memories in recent years, raster scanning color graphic display systems having a large capacity bit map memory plane are becoming more compact and less 10 expensive. Such a color graphic display comprises three bit map memory planes respectively corresponding to three primary colors, i.e., red, green and blue, a function generator and a microprocessor. When displaying a graphic pattern in the graphic color display system, the 15 function generator is made to generate display information, which is successively developed into the respective memory planes and is then cyclically read in synchronism with the raster scanning, and is transferred to a CRT monitor to result in the desired display. 20
During the display, logical or arithmetic operations are frequently conducted on the contents read out of the memory locations of the memory planes of the same or corresponding picture elements.
For instance, in a color display apparatus, there may 25 be provided three memory planes for storing data of the three primary colors, and it may be desired to form an image pattern consisting of the area on which two or more colors are superimposed or mixed, or to select the area of a single specific color. In such cases, it is neces- 30 sary to perform logical operations on the data from the memory planes.
To meet the need of logical operations, a conventional picture display apparatus generally employs a high-speed microprocessor which sequentially reads 35 the data from the memory planes and performs logical operations on the data read out.
Such an arrangement is satisfactory small capacity memory planes. But with memory planes of a large capacity, e.g., 1024x1024 dots, it takes a long time for 40 the microprocessor to read the data from the memory planes and to conduct the logical operations on the data read out, so that the performance of the overall device is limited.
SUMMARY OF THE INVENTION 45
An object of the invention is to provide a display apparatus with which it is possible to reduce the burden on the microprocessor when logical operations are performed on the data read out of the memory planes, 50 thereby raising the processing speed.
According to the invention, there is provided display apparatus comprising:
a plurality of memory planes for storing data for display, 55
graphic display control means for writing data in and reading data out from the memory planes,
a data processing unit for controlling the memory planes and the graphic display control means,
a system bus for connecting the data processing unit 60 and the graphic display control means,
a display bus for connecting the graphic display control means and the memory planes,
a logical operation circuit capable of performing logical operation in a plurality of different modes of 65 operation,
mode registration means for latching a mode of operation designated by the data processing unit, an instruc
tion for the designation being supplied through the system bus,
the logical operation circuit being controlled to perform, in the mode latched in the mode registration means, logical operation on the data read from the memory planes, and
a selector receiving data read from the memory planes and data outputted from the logical operation circuit, and making selection in accordance with designation from the data processing unit, and outputting the selected data to the display bus.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a block diagram showing part of the display apparatus according to the invention;
FIG. 2 is a time chart showing the operation of the display apparatus; and
FIGS. 3 and 4 are diagrams showing how the pattern of white is extracted by the display apparatus.
DETAILED DESCRIPTION OF THE
FIG. 1 shows an essential part of a display apparatus 3 of an embodiment of the invention. The display apparatus 3 is connected to a host computer 1 via a communication cable 2.
The display apparatus 3 comprises, as is conventional, a data processing unit such as a microprocessor 4 connected to the communication cable 2 and controlling the rest of the display apparatus 3, a bidirectional bus driver (system bus) 5 connected to the microprocessor 4, a graphic display controller (hereinafter referred to as GDC) 6 connected to the bus driver 5, and three memory planes 8,9,10 connected to the GDC via an address register 7 and a CRT bus (display bus). The memory planes 8, 9, 10 store data of three primary colors, i.e., red, blue and green, on a bit-by-bit basis. The address register 7 stores an address of the locations in the memory planes to be accessed. The GDC 6 writes data in and reads data out from the memory planes thereby controlling drawing of data and display of data by a CRT (cathode ray tube) monitor 16. The data outputted from each of the memory planes 8, 9, 10 is in the form of 1 byte (8 bits) of parallel data indicative of the level "1" or "0" of each of 8 dots adjacent to each other and aligned in a horizontal direction. Shift-registers 11, 12, 13 are connected to the memory planes 8, 9,10, respectively, and perform parallel-to-serial conversion to convert the parallel data from the memory planes 8,9,10 to serial data. The outputs of the shift registers 11, 12, 13 are supplied to the CRT monitor 16 for display on its display screen. The display apparatus 3 further comprises a timing control circuit 17 generating timing signals used for control of the various components of the display apparatus. The timing signals include a clock signal CCLK comprising elementary clocks <f>i, <|>2, <f>3
The microprocessor 4 transfers display information via the bidirectional bus driver 5 and also sets parameters in the GDC 6 to define the screen arrangement. The GDC 6 conducts movement in accordance with the parameter data, writes picture element information in the memory planes 8, 9, 10 corresponding to the primary colors, and performs reading operations for the purpose of display in cooperation with various timing signals outputted from the timing control circuit 17.