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(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2004/0130561 Al
Jain (43) Pub. Date: Jul. 8,2004
(54) MASKLESS LITHOGRAPHY WITH MULTIPLEXED SPATIAL LIGHT MODULATORS
(76) Inventor: Kanti Jain, Briarcliff Manor, NY (US)
Carl C. Kling, General Counsel
6 Skyline Drive
Hawthorne, NY 10532 (US)
Imaging systems that use a spatial light modulator (SLM), such as maskless lithography systems using a digital micromirror device (DMD), suffer from low throughput at high resolution because of the increase in the number of pixels to be imaged. A possible solution to this problem is provided by using multiple SLMs. However, packaging multiple SLMs on a suitable base is inefficient because, in an SLM, surrounding the active region, a large inactive region is required for the chip kerf and the connector fan-in; these inactive regions thus prevent close packing of the SLMs. This invention enables close packing of a large number of SLMs by arranging them in twin planes, such that the kerf and fan-in regions overlap substantially. Variations in the optical conjugate distances of different SLMs caused by the twin planarity are eliminated by incorporation of a twinpane compensating mirror array that corresponds to the SLM array, and introduces a pathlength difference between different mirrors that is complementary to the pathlength difference between corresponding SLM chips. Depth-offocus problems are thus eliminated. The invention enables significant throughput enhancement, up to 82%, in maskless lithography systems.
MASKLESS LITHOGRAPHY WITH MULTIPLEXED SPATIAL LIGHT MODULATORS
FIELD OF THE INVENTION
 The invention relates to an optical patterning system using multiple reflective spatial light modulator (RSLM) chips, and more particularly relates to a very high throughput, large-area maskless lithography system, using multiple RSLM chips mounted in plural planes with partial overlapping for closer RSLM chip packing and higher throughput, and using related auxiliary mirrors in complementary plural planes to compensate for pixel beamlet length variations from multi-planar RSLM chip placement.
DESCRIPTION OF RELATED ART
 A variety of spatial light modulator (SLM) types, some transmissive and some reflective, are currently available. Preferred is a reflective SLM (RSLM) of the digital micromirror device (DMD chip) in which an array of micromirrors mounted in an x-y array of rows and columns can serve as individually selectable multiple beam devices. Each micromirror element has an x-y address selected by electrical signals to remain flat when unselected, or tilt when selected. A state-of-the-art DMD chip has an array of approximately 800x1000 micromirrors with associated addressing and other connections for pixel selection. Pixel selection can be accomplished very quickly and with good certainty, in a refresh time between light pulses applied to the DMD array on the chip. A micromirror element selected during such a refresh time serves to redirect its assigned pixel beamlet to a related selected pixel in the image plane for use.
 A DMD chip with an array of 800x1000 pixels may have an active mirror array of 1.2x1.4 cm with 0.2 cm or wider borders. The border regions contain addressing electronics and allow a small space tolerance for dicing losses. In addition, such RSLM chips typically require an additional fan-in area, typically off-chip on a circuit board module, the module typically being more than three times the size of the RSLM chip in each dimension.
 It is possible to mount a number of DMD chips, with associated fan-out boards, side-by-side on a suitable substrate, typically a polymer, silicon or glass wafer, to achieve a high-throughput, large-area imaging capability. While the active mirror portions of the DMD chips have very dense pixel packing, there are significant area losses due to kerf areas and fan-out boards. As already stated, the kerf areas are required for power, for addressing, and to permit chip dicing. The fan-in areas are required because of the very large number of addressing signals and power inputs required.
 As an example, we calculate the packing efficiency of standard DMD chips with border regions, using a chip size of 1.2x1.4 cm and kerf regions of 3 mm width.
Area of active mirror array=1.2xl.4=1.68 cm2
Kerf region width=0.3 cm
Area of total array package=1.8x2.0=3.60 cm2
 The above packing efficiency is further harmed when the fan-in area of the connector module is taken into
account. As an example, if we take a fan-in module size of 3.0 cmx2.8 cm=8.4 cm2, it will reduce this 46.7% packing efficiency to 1.68/8.4=20%.
 Packing efficiency might be incremented somewhat by use of a larger DMD chip. Addressing realities, however, might require that the larger chip have a wider kerf to accommodate the greater addressing requirements. In any case, changes by the DMD manufacturer might be uneconomical just to increase the packing efficiency marginally. The favored choice is to use standard DMD chips where possible.
BRIEF SUMMARY OF THE INVENTION
 The invention is a maskless lithography system using SLMs, such as DMD chips, mounted in close-packed twin-plane multiplex subassemblies, with partial overlap of DMD chips, and with focus-compensation related to the multiplanarity. The partial-overlap technique permits closer packing of DMD chips by overlapping the inactive kerf areas while leaving active mirror areas undisturbed, to reflect incident radiation. The partial-overlap technique adds approximately 15% to the packing density and 33% to the lithography system throughput. This enhancement becomes significantly greater when the fan-in regions for the connectors are taken into consideration. For example, for a module size of 3.0 cmx2.8 cm=8.4 cm2 and the DMD size same as before (1.4 cmxl.2 cm=1.68 cm2), the packing efficiency becomes 1.68/8.4=20.0%. With the twin-plane packing technique of this invention, this efficiency increases to 36.4%, giving a throughput increase of 36.4/20.0=1.82=82%. The partial-overlap technique, however, places half the DMD chips in a base plane and the other half of the DMD chips in an alternate plane, with the base plane and the alternate plane being parallel but spaced apart by the thickness T of the DMD elements plus tolerances (T+t). This spacing (T+t) would, without compensation, cause there to be two different pixel beamlet lengths which would overwhelm the required depth of focus requirements of the system. This invention provides such compensation, appropriate in positioning and spacing, so as to maintain a fixed pixel beamlet length for each of the myriad pixel beamlets.
 The object of the invention is to provide a means for performing maskless lithography by multiplexing an array of n separate DMD chips, each with multiple thousands (m) of individually-addressable pixel-selection mirrors, to provide via a reducing production lens an in-focus highly-reduced patterning image at the substrate of (nxm) pixel beams. Focus lost by the multi-plane positioning of partially-overlapped DMD chips is regained by using a twin-plane set of mirrors with complementary multi-plane positioning. Each partially-overlapped DMD chip sends data-selected pixel beamlets to a complementary twin-plane set of mirrors, each mirror matching a related DMD chip in x-y size and position while being positioned complementarily in z depth. The individual mirror compensates for pixel-beamlet-lengfh at the input to the projection lens.
 A feature of the invention is that the pixel-selection capability of multiple DMD arrays per unit area is enhanced by approximately 15%, without altering the apparent pixelbeamlet-length, because the compensating mirrors maintain focus within depth-of-focus tolerances during pixel selection.