![[graphic]](http://www.google.com/patents?id=MZITAAAAEBAJ&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=en&q=5,941,947&cds=1&sig=ACfU3U3jTpZB0Jd8FN-6qyo_XjBoXpoM1Q&edge=0&edge=stretch&ci=372,739,59,53)
![[graphic]](http://www.google.com/patents?id=MZITAAAAEBAJ&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=en&q=5,941,947&cds=1&sig=ACfU3U3jTpZB0Jd8FN-6qyo_XjBoXpoM1Q&edge=0&edge=stretch&ci=760,251,51,14)
![[graphic]](http://www.google.com/patents?id=MZITAAAAEBAJ&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=en&q=5,941,947&cds=1&sig=ACfU3U3jTpZB0Jd8FN-6qyo_XjBoXpoM1Q&edge=0&edge=stretch&ci=762,339,45,29)
(12) United States Patent (10) Patent No.: US 6,887,800 B1 Metz et al. (45) Date of Patent: May 3, 2005 (54) METHOD FOR MAKING A 6,475,874 11/2002 Xiang et al. .............. .. 438/396 SEMICQNDUCTQR DEVICE WITH A HIGH- 6,514,828 2/2003 Ahn et al. ................ .. 438/240 K GATE DIELECTRIC AND METAL LAYERS 6,544,906 4/2003 Rotondaro et al. ....... .. 438/785 THATMEMAP/N 2888 3/522; a1:.:;:;~. ~~~~~~~~~~~~~~~~ ~11;2/as . 626172210 9/2003 Ch r 1. ............... .. 438/240 (75) Invenmrsi Matthew V‘ Metz’ H1HSb9r9’ OR (US); 6 620713 9/2003 Argifiaf/aiii et al. ........ .. 438/585 Slime“ Dam» B°a"@ii°“> OR (U5); 676427131 * 11/2003 Harada ..................... .. 438/591 Jaek Ka"aiieY°$> P01111191 QR (U5); 6:667:246 * 12/2003 Mitsuhashi et al. ....... .. 438/756 Mark L- Doczy, Beaverton, OR (US); 6,689,675 2/2004 Parker et al. ............. .. 438/585 Justin K. Brask, Portland, OR (US); 6,696,327 2/2004 Brask et al. .... .. 438/197 Uday Shah, Portland, OR (US); Robert 6,696,345 2/2004 Chau et al. . 438/387 S_ Chan, Beaverton, OR (US) 2002/0058374 5/2002 Kim et al. ................ .. 438/228 2002/0197790 12/2002 Kizilyalli et al. ......... .. 438/240 (73) Assignee: Intel Corporation, Santa Clara, CA 2003/0032303 2/2003 Yu et al. ................... .. 438/770 (US) 2003/0045080 3/2003 Visokay et al. ........... .. 438/591 FOREIGN PATENT DOCUMENTS ( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 EP 0 899 784 AZ 3/1999 U_S_C_ 154(b) by Q dayS_ GB 2 358 737 A 4/2001 OTHER PUBLICATIONS (21) Appl. No.: 10/862,169 _ Polishchuk et al., “Dual Workfunction CMOS Gate Tech(22) Fiiedi Jun‘ 4’ 2004 nology Based on Metal Interdiffusion”, vvvvW.eesc.berke(51) Int. cl.’ ...................... .. H01L 21/31, H01L 21/469 i°Y~°‘i“» 1 Pag“’~ (52) U.S. Cl. ..................... .. 438/778; 438/591; 438/785; (Continued) 438/216; 438/287 (58) Field of Search ............................... .. 438/216, 287, Primary Examiner—Michael Tran 438/591, 778, 785 Assistant Examiner—Renee R. Berry (74) Attorney, Agent, or Firm—Mark V. Seeley (56) References Cited (57) ABSTRACT U.S. PATENT DOCUMENTS _ _ _ _ _ A method for making a semiconductor device is described. 6963598 A 5/2000 Tseng _ei ai~ ~~~~~~~~~~~~~~ ~~ 438/585 That method comprises modifying a first surface, and form9>184>O72 B1 2/2001 Kaushlk 91 91" 438/197 ing a high-k gate dielectric layer on an unmodified second 6,255,698 B1 7/2001 Gardner et al. . . . . . . . . .. 257/369 Surface 6,365,450 B1 4/2002 Kim ......... .. 438/216 i 6,410,376 B1 6/2002 Ng et al. 438/199 6,420,279 B1 7/2002 Ono et al. ................ .. 438/785 6 Claims, 3 Drawing Sheets
![[graphic]](http://www.google.com/patents?id=MZITAAAAEBAJ&ie=ISO-8859-1&output=text&pg=PA1&img=1&zoom=3&hl=en&q=5,941,947&cds=1&sig=ACfU3U3jTpZB0Jd8FN-6qyo_XjBoXpoM1Q&edge=0&edge=stretch&ci=167,848,635,289)
![[merged small][graphic]](http://www.google.com/patents?id=MZITAAAAEBAJ&ie=ISO-8859-1&output=text&pg=PA2&img=1&zoom=3&hl=en&q=5,941,947&cds=1&sig=ACfU3U3q01_6-bgZgQ6B8h5tkUSAq0z9Mw&edge=0&edge=stretch&ci=127,115,733,22)
Doug Barlage et al., High-Frequency Response of 100nm Integrated CMOS Transistors With High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page. Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies With Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
U.S. Appl. No. 10/327,293, filed Dec. 20, 2002, Doczy et al., “Integrating N-type and P-type Metal Gate Transistors”. U.S. Appl. No. 10/704,497, filed Nov. 6, 2003, Brask et al., “A Method for Making a Semiconductor Device Having a Metal Gate Electrode”.
U.S. Appl. No. 10/704,498, filed Nov. 6, 2003, Brask et al., “A Method for Etching a Thin Metal Layer”.
U.S. Appl. No. 10/742,678, filed Dec. 19, 2003, Brask et al., “A Method for Making a Semiconductor Device With a Metal Gate Electrode that is Formed on an Annealed High-K Gate Dielectric Layer”.
U.S. Appl. No. 10/739,173, filed Dec. 18, 2003, Brask et al., “A Method for Making a Semiconductor Device that includes a Metal Gate Electrode”.
U.S. Appl. No. 10/748,559, filed Dec. 29, 2003, Brask et al., “A CMOS Device With Metal and Silicide Gate Electrodes and a Method for Making It”.
U.S. Appl. No. 10/748,545, filed Dec. 29, 2003, Doczy et al., “A Method for Making a Semiconductor Device that Includes a Metal Gate Electrode”.
U.S. Appl. No. 10/805,880, filed Mar. 22, 2004, Shah et al., “A Method for Making a Semiconductor Device With a Metal Gate Electrode”.
U.S. Appl. No. 10/809,853, filed Mar. 24, 2004, Shah et al., “A Replacement Gte Process for Making a Semiconductor Device that Includes a Metal Gate Electrode”.
U.S. Appl. No. 10/898,958, filed Apr. 20, 2004, Brask et al., “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode”. U.S. Appl. No. unknown, filed May 4, 2004, Metz et al., “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric Layer and a Metal Gate Electrode”. U.S. Appl. No. unknown, filed May 26, 2004, Brask et al., “A Method for Making a Semiconductor Device With a High-K Gate Dielecteic and a Conductor that Facilitates Current Flow Across a P/N Junction”.
U.S. Patent May 3,2005 Sheet 2 0f3 US 6,887,800 B1
|
