US 20030227405A1
(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2003/0227405 Al
Nakamoto (43) Pub. Date: Dec. 11,2003
(54) INTERPOLATION CIRCUIT HAVING A
CONVERSION ERROR CORRECTION
RANGE FOR HIGHER-ORDER BITS AND
A/D CONVERSION CIRCUIT UTILIZING
THE SAME
(75) Inventor: Hiroyuki Nakamoto, Kawasaki (JP)
Correspondence Address:
ARENT FOX KINTNER PLOTKIN & KAHN
1050 CONNECTICUT AVENUE, N.W.
SUITE 400
WASHINGTON, DC 20036 (US) (73) Assignee: FUJITSU LIMITED
(21) Appl. No.: 10/454,694
(22) Filed: Jun. 5, 2003
(30) Foreign Application Priority Data
Jun. 5, 2002 (JP) 2002-164829
Publication Classification (51) Int. CI.7 II03M 1 12
An interpolation circuit for generating interpolation and extrapolation differential voltages to a first and second differential input voltages, comprises a first and second differential amplifiers for inputting the first and second differential input voltages, respectively, and for generating a differential output voltage respectively between their inverted output terminal and their respective non-inverted terminal. The interpolation circuit further comprises a first voltage dividing element array disposed between the noninverted output terminals of the first and second differential amplifiers, and a second voltage dividing element array disposed between the inverted output terminals of the first and second differential amplifiers, so that the interpolation differential voltages are generated from nodes in the first voltage dividing element array and nodes in the second voltage dividing element array. The interpolation circuit further comprises a third voltage dividing element array disposed between the inverted output terminal of the first differential amplifier and the non-inverted output terminal of the second differential amplifier, so that at least a pair of extrapolation differential voltages are generated from nodes in the third voltage dividing element array.
