(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2002/0177266 Al
Klein et al. (43) Pub. Date: Nov. 28,2002
(54) SELECTABLE OUTPUT EDGE RATE CONTROL
(76) Inventors: Christian Klein, Portland, ME (US);
Myron J. Miske, Newfields, NH (US)
CESARI AND MCKENNA, LLP
88 BLACK FALCON AVENUE
BOSTON, MA 02210 (US)
(21) Appl. No.: 10/153,449
(22) Filed: May 22, 2002
Related U.S. Application Data
(60) Provisional application No. 60/293,361, filed on May 24, 2001.
Publication Classification (51) Int. CI.7 H01L 21/8238
A circuit using current starved pull up and pull down transistors is arranged to connect a current source via each transistors to an output transistor stage. The current source values are selected so that the starved transistors provide a known voltage edge rate profile as a function of the current sources and the parameters of the transistors. Two or more additional current sources, that when enabled contribute current in parallel with the first current sources such that controlled edge rate profiles are selectively speeded up in response the enabled current sources. An enable input is provided for each additional current source for selectably controlling the faster or slower edge rate profiles. Reference voltages are used to determine the current source values along with transistor parameters. Preferably the transistor are MOSFETs.