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United States Patent [w]
 OUTPUT DRIVER FOR SUB-MICRON CMOS
 Inventor: Donald M. Bartlett, Fort Collins, Colo.
 Assignee: LSI Logic Corporation, Milpitas, Calif.
 Appl. No.: 08/772,617  Filed: Dec. 23, 1996
 Int. CI.6 H03K 19/0185
 U.S. CI 326/81; 326/83; 326/68
 Field of Search 326/70, 71, 68,
326/80, 81, 83, 86
 References Cited
U.S. PATENT DOCUMENTS
4,847,522 7/1989 Fuller et al 326/81
5,173,624 12/1992 Gabillard et al. .
5,179,299 1/1993 Tipon .
5,300,832 4/1994 Rogers 326/68
5,313,118 5/1994 Lundberg .
5,378,943 1/1995 Dennard 326/81
5,381,055 1/1995 Lai et al 326/27
5,381,059 1/1995 Douglas 326/58
5,399,920 3/1995 Tran 326/83
5,406,139 4/1995 Sharpe-Geisler 326/71
5,428,303 6/1995 Pasqualini 326/27
5,440,249 8/1995 Schucker et al 326/83
5,444,397 8/1995 Wong et al 326/81
5,467,313 11/1995 Jung et al 365/189.11
5,483,454 1/1996 Hawkins et al 326/81
5,559,464 9/1996 Orii et al 326/81
5,675,278 10/1997 Tanaka et al 326/83
5,684,415 11/1997 McNamus 326/27
FOREIGN PATENT DOCUMENTS
194134 9/1986 European Pat. Off. .
630110 12/1994 European Pat. Off. .
Ohtomo Y. et al; "A Quarter-Micron SIMOX-CMOS LVT-
TL-Compatible Gate Array with an Over 2,000 V ESD-
-Protection Circuit"; May 5, 1996; pp. 57-60.
"5-Volt Signal Level Shifter in a 3-Volt CMOS Circuit";
IBM Technical Disclosure Bulletin, vol. 32, No. 7, Dec. 1,
1989, pp. 454/455.
Primary Examiner—-Jon Santamauro
Assistant Examiner—Don Phu Le
Attorney, Agent, or Firm—David K. Lucente
An on-chip driver is described for applications voltage output signals are desired from a digital sub-micron CMOS integrated circuit. The driver includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output-up down and the level shifter. The output pulldown is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level of about 0 volts when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up which pulls the output of the driver to a high voltage level of 2.5 volts or greater when the digital CMOS input is at a high logic state.
29 Claims, 2 Drawing Sheets
OUTPUT DRIVER FOR SUB-MICRON CMOS
FIELD OF THE INVENTION
The present invention relates to complementary MOS (CMOS) integrated circuit technologies, and in particular to 5 sub-micron CMOS having an output driver that provides a digital logic output voltage.
BACKGROUND OF THE INVENTION
There are generally three logic families for use in digital 1° systems: transistor-transistor logic (TTL), complementary metal-oxide semiconductor logic (CMOS), and emittercoupled logic (ECL). The use of a particular logic family within an electrical design is governed mainly by design considerations such as speed, power consumption, noise :5 immunity, cost, availability, and ease of interfacing with other logic families.
TTL has been the most widely used logic family for many years in applications that use small-scale integration and medium-scale integration. The TTL family is powered by a 20 supply voltage of five volts. Correspondingly, there is a proliferation of systems in the electronics industry which utilize five volt power supplies as either the main power supply or at least one of the primary power supplies.
There are many integrated circuits (ICs) within the CMOS logic family that are compatible (i.e., five volt compliant) with TTL. This allows for the introduction of both TTL and CMOS integrated circuits within an electrical design without the need to provide additional circuitry to interface the ^ different logic families together.
In many cases, the digital output signal of a CMOS integrated circuit is made TTL compatible by using a standard CMOS inverter, scaled appropriately to drive an off-chip TTL load, as a pad driver which is bonded to the pin 35 of the CMOS integrated circuit package. The pin of the CMOS integrated circuit is connected to other integrated circuits by means of a system board such as a printed circuit board (PCB).
It is well known that CMOS integrated circuits with gate 40 oxides thicker than approximately 120 Angstroms can safely and reliably operate with a supply voltage of five volts. However, in the semiconductor industry there has emerged a trend toward the development of low voltage, high-density, sub-micron processing technologies. Thus, as CMOS inte- 45 grated circuit technologies continue to shrink in physical size, the supply voltage that these processes are capable of supporting is also reduced.
For instance, in a sub 0.5mm CMOS process, the gate oxide is often reduced to 90 Angstroms which is not capable 50 of supporting a five volt power supply in a reliable fashion. Long term exposure of such a small geometry gate oxide to a voltage greater than 3.3 volts can lead to failure of the CMOS integrated circuit. Nevertheless, some systems that include smaller geometry silicon integrated circuits are still 55 operated with a supply voltage of five volts.
To reduce the stress on the smaller geometry integrated circuits, digital libraries have been developed which operate with supply voltages of 3.3 volts or less, rather than at the traditional five volt level. However, it has not been possible 60 to convert all the myriads of electronic devices to operate by using less than five volts. For example, a newer sub-micron CMOS microprocessor may operate at 3.3 volts while the only I/O buffers available to use with the microprocessor are 5-volt ICs from the TTL logic family. Thus, some ICs in the 65 circuit design may require a supply voltage of five volts while others must operate at 3.3 volts.
If both 5 volt integrated circuits and 3.3 volt sub-micron integrated circuits are used in an electrical design, then additional measures must be taken to interface the circuits together. These extra steps are needed since smaller geometry integrated circuits are precluded from driving out a true five volt logic signal because of their reduced voltage restriction. Thus, voltage level translators or shifters are required between those sub-micron integrated circuits operating at 3.3 volts and those integrated circuits operating at five volts.
A typical solution to the above-stated voltage level shifting problem is to use special level shifter ICs between the circuits having five volt logic inputs and the 3.3 volt sub-micron CMOS outputs. The level shifter ICs are capable of responding to a low voltage swing (3.3 volts) digital input and driving out a full five volt output signal. However, such level shifters are fabricated using a larger geometry CMOS process (i.e., larger than sub-micron) or some other silicon process capable of supporting both five volt supply voltages and five volt gate oxide voltages.
Another alternative to the level shifting problem is to drive a five volt powered CMOS integrated circuit directly with the output of a 3.3 volt sub-micron integrated circuit and adjust the threshold levels of the five volt powered CMOS device to accept the reduced output voltage swing of the 3.3 volt device. However, in some cases, reducing the input threshold levels of existing integrated circuits can be costly.
The present invention overcomes the above-discussed problems by providing a sub-micron CMOS output driver that can generate a five volt digital output without overstressing the gate oxides of the driver.
SUMMARY OF THE INVENTION
The present invention provides a digital output driver fabricated by a sub-micron CMOS process.
The on-chip structure embodying the present invention is especially suitable for applications wherein five volt logic output signals are desired from a sub-micron CMOS integrated circuit. The present invention allows for small geometry integrated circuits to directly interface with five volt devices. As such, the present invention eliminates the need for either adding voltage level shifters to the system board or requiring that the input threshold levels of existing five volt components be redesigned.
The output driver embodying the present invention is fabricated by a sub-micron CMOS process and includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output pull-down and the level shifter. The output pull-down is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up that pulls the output of the driver to a high voltage level when the digital CMOS input is at a high logic state.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings that form part of the specification, and in which like numerals are employed to designate like elements throughout the same,
FIG. 1 is a block diagram illustrating an output driver for sub-micron CMOS in accordance with the present invention; and