QUATERNARY PHASE-SHIFT KEYING WITH TIME DELAYED CHANNEL
BACKGROUND OF THE INVENTION
Digital communication is often accomplished by phase modulation of a carrier with either 0° or 180° of phase shift corresponding to a logic state of 0 or 1. Frequently, two such communication channels utilizing carriers which are phase shifted from each other by 90° are employed. The two channels are summed together to give a resultant carrier which experiences phase modulation of ±45° or ±135°, these four possible phase states representing the two logic states in each of the two channels. The resultant phase-modulated carrier is referred to as being modulated by quaternary phaseshift keying (QPSK). Such a system is described in the book entitled "Data Transmission" by William R. Bennett and James R. Davey which was published by McGraw-Hill Book Company in 1965. .
A QPSK modulated carrier is frequently transmitted via a microwave radio link at a carrier frequency of, for example, 10 gigahertz (gHz). In order to provide suitable power of radiated energy in a microwave transmission link, an injection-locked oscillator is often employed. An injection-locked oscillator type of amplifier is convenient to use because of its physically small size, it being composed of, essentially, a diode affixed within a suitably tuned portion of a waveguide with a voltage applied across the diode from an external source of electric power.
A problem arises when the injection-locked oscillator type of amplifier is employed with a QPSK modulated carrier, the problem being that a quantum phase shift of 180° frequently occurs. Such an occurrence is characterized in a typical communication system by a momentary drop in the amplitude of the modulated carrier with the result that the oscillation of the amplifier loses lock with respect to the modulated carrier. Ideally, the injection-locked oscillator is tuned to oscillate at the carrier frequency of the signal to be amplified as this relationship provides for maximum efficiency of the amplification process. Unfortunately, this frequency relationship intensifies the foregoing problem. Attempts to alleviate the problem of offsetting the oscillation frequency from that of the signal to be amplified degrades the quality of the amplification in that there is a loss of phase coherence between the input and output of the amplifier with attendant phase errors. As a result, the usefulness of the injection-locked oscillator is greatly reduced in the situation where it is desired to transmit accurate data via a QPSK modulated carrier.
SUMMARY OF THE INVENTION
The aforementioned problem is overcome and other advantages are provided by a communication system employing QPSK modulation of a carrier which is derived from a first carrier and a second carrier is quadrature therewith, said first and second carriers being modulated with digital data in a binary phase format of 0° and 180°. In accordance with the invention, a time delay equal to approximately one-half the width of a pulse representing a bit of the digital data is provided between the digital modulation of one of the two carriers and the digital modulation of the second carrier. Thereby, a transition in the phase modulation of one carrier occurs before a phase transition in the modulation of the second carrier. Thus, upon summing to
gether the first and the second carriers to produce the QPSK modulated carrier of the microwave link, the quantum phase shifts resulting from the modulation never exceed a value of 90°. A microwave amplifier
5 employing an injection-locked oscillator has been found to respond successfully to phase transitions to 90° and, accordingly, a QPSK communication system employing the interchannel delay of this invention has successfully operated with an injection-locked ampli
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned aspect and other features of the invention are explained in the following description 15 taken in connection with the accompanying drawings wherein;
FIG. 1 is a block diagram of a communication system embodying the invention; and FIG. 2 is a timing diagram useful in explaining the 20 operation of the system of FIG. 1.
DESCRIPTION OF THE PREFERRED
Referring now to FIG. 1, there is seen a block dia25 gram of a communication system 20 which comprises two digital data sources 22 and 24, two phase modulators 26 and 28, an oscillator 30 which provides a sinusoidal carrier signal of intermediate frequency to the phase modulator 26, a phase shifter 32 for coupling the 30 carrier from the oscillator 30 to the phase modulator 28, and a summer 38 for summing together the output signals of the modulators 26 and 28. The phase shifter 32 imparts a phase shift of 90° to the carrier of the oscillator 30 and provides a reference carrier on line 34 35 to the modulator 28 which is in phase quadrature to the reference carrier on line 36 applied to the modulator 26.
In accordance with the invention, there is provided a delay unit 40 for coupling digital data from the source
40 24 to the modulator 28. The digital data from both the sources 22 and 24 is in the form of binary data having logic states of 0 and 1 which correspond respectively to a low voltage and a high voltage. A clock 42 provides clock pulses at a frequency F and period T, these clock
45 pulses being coupled by a divider 44 to the data sources 22 and 24 for synchronizing their operation. The divider 44 divides the rate of clock pulses by two so that the clock pulses coupled on line 46 to the sources 22 and 24 occur at one-half the rate of clock pulses cou
50 pled via the clock 42 along line 48 to the delay unit 40. The binary data signals of the source 22 are clocked onto line A by the clock pulses on line 46 and, similarly, the binary data signals of the source 24 are clocked onto line B by the clock pulses on line 46. The
55 binary data of line B is delayed by a duration of onehalf the duration of one bit of the binary data before being coupled via line C to the modulator 28.
The delay unit 40 is in the form of a single cell shift register which is clocked by pulses on line 48 at twice
60 the rate of the clocking of the digital data by the pulses on line 46. Each bit of the digital data has a duration of 2T while the duration of the delay is T. Thus, each time a bit of digital data appears on line B, the same bit reappears on line C after a delay of T seconds.
65 The modulator 26 modulates the phase of the carrier of line 36 with the binary formated digital data of line A while the modulator 28 modulates the carrier on line 34 with the binary formated data on line C. The modu