US 20020087708A1
(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2002/0087708 Al
Low et al. (43) Pub. Date: Jul. 4,2002
(54) METHOD OF PROCESSING SERIAL
DATA,SERIAL DATA PROCESSOR AND
ARCHITECTURE THEREFORE
(76) Inventors: Arthur John Low, Chelsea (CA);
Stephen J. Davis, Nepean (CA)
Correspondence Address:
Gordon Freedman
Freedman & Associates
Suite 350
117 Centrepointe Drive
Nepean, ON K2G 5X3 (CA)
(21) Appl. No.: 09/741,829
(22) Filed: Dec. 22, 2000
Publication Classification
(51) Int. CI.7 G06F 15/16; G06F 5/00;
G06F 3/06; G06F 3/05; G06F 3/023;
G06F 3/00; G06F 3/02; G06F 15/173
(52) U.S. CI 709/231; 709/238
(57) ABSTRACT
A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list processes to perform on the packet of data and am ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is not next process for a packet at which time it is provided to an output port.
