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United States Patent [w]
US005861773A [ii] Patent Number: 5,861,773  Date of Patent: Jan. 19, 1999
 CIRCUIT FOR DETECTING THE LOCKED CONDITION OF PSK OR QAM
 Inventor: Jacques Meyer, Corenc, France
 Assignee: SGS-Thomson Microelectronics SA.,
Saint Genis, France
 Appl. No.: 982,979
 Filed: Dec. 2, 1997
Related U.S. Application Data
 Continuation of Ser. No. 675,632, Jul. 1, 1996, Pat. No. 5,703,526.
 Foreign Application Priority Data
Jul. 6, 1995 [FR] France 95 08401
 Int. C I. H04L 27/22
 U.S. CI 329/304; 329/308; 331/DIG. 2;
 Field of Search 329/304, 308,
329/309; 331/DIG. 2; 375/326, 327, 328,
 References Cited
U.S. PATENT DOCUMENTS
4,057,762 11/1977 Namiki 375/376
4,736,386 4/1988 Nichols 375/224
4,853,642 8/1989 Otani et al 329/306
4,870,382 9/1989 Keate et al 331/4
4,958,360 9/1990 Sari 375/344
4,987,375 1/1991 Wu et al 329/309
5,121,071 6/1992 Kelly et al 329/307
FOREIGN PATENT DOCUMENTS
C-42 16 156 8/1993 Germany .
IEEE Transactions on Communication, vol. 30, No. 10, Oct. 1982 New York, US, pp. 2385-2390, Yoshio Matsuo & Junji Namiki, "Carrier Recovery Systems For Arbitrarily Mapped APK Signals".
Primary Examiner—Siegfried H. Grimm
Attorney, Agent, or Firm—-Woll, Greenfield & Sacks, PC.
A method for detecting a locked condition ol a demodulator ol at least one signal that may have discrete levels defining a constellation ol nominal points in a plane. The method includes the steps ol defining relerence areas about the nominal points, a relerence area being separated Irom another by a band or an angular sector crossing the origin ol the constellation plane, and indicating a locked condition il the ratio ol points occurring in the relerence areas is above the probability for points to occur in the relerence area, when the demodulator is wrongly adjusted.
6 Claims, 2 Drawing Sheets
U.S. Patent Jan. 19,1999 sheet 1 of 2 5,861,773
U.S. Patent Jan. 19,1999 sheet 2 of 2 5,861,773
CIRCUIT FOR DETECTING THE LOCKED
CONDITION OF PSK OR QAM
This application is a continuation of application Ser. No. 08/675,632, filed Jul. 1, 1996, entitled A CIRCUIT FOR 5 DETECTING THE LOCKED CONDITION OF PSK AND QAM DEMODULATORS, now U.S. Pat. No. 5,703,526.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to PSK (Phase-Shift Keying) and QAM (Quadrature Amplitude Modulation) modulation techniques for simultaneously transmitting a plurality of bits. The present invention more particularly ^ relates to the detection of the locked condition of PSK or QAM demodulators.
2. Discussion of the Related Art
FIG. 1 schematically represents a conventional QPSK (Quadrature PSK) demodulator. Such a QPSK demodulator 20 is used to extract from a signal Sm two binary signals I and Q modulated in phase quadrature. Signal Sm is generally expressed by I cos wt+Q sin cot, where cos cot and sin exit are two carriers having the same frequency cti/2it, but are in phase quadrature. Signal Sm is applied to two multipliers 10 25 and 11 which further receive signal cos exit and signal sin co, respectively, provided by a voltage controlled oscillator (VCO) 13 connected in a phase-locked loop (PLL). If the frequency of oscillator 13 is close to the frequency of the carrier, multiplier 10 provides a signal having a mean value 30 corresponding to signal I and an a.c. component whose frequency is twice the carrier's frequency. Similarly, multiplier 11 provides a signal having a mean value corresponding to signal Q and an a.c. component whose frequency is twice the carrier's frequency. Low-pass filters 15 eliminate 35 the a.c. components of the outputs of multipliers 10 and 11 and respectively provide signals I and Q.
A phase detector 17 receives signals I and Q and provides a signal c|) indicative of the phase error of signals I and Q. Signal (|) controls the frequency of oscillator 13 so that the 40 phase difference c|) tends to zero. Generally, signal c|) is applied to oscillator 13 through a low-pass filter 19 whose cut-off frequency is very low so that oscillator 13 is only controlled by the mean variations of signal c|).
FIG. 2A illustrates a conventional representation, in the form of a "constellation", of the possible combinations of the demodulated binary signals I and Q. The values of signal I are read along a horizontal axis I, and the values of signal Q are read along a vertical axis Q. In QPSK modulation, 5Q each signal I and Q has a positive value or a negative value of the same amplitude, corresponding to the high and low logic levels. The nominal constellation, corresponding to the case where the signals provided by oscillator 13 are in phase with the two carriers in quadrature, includes four points 5J P1-P4 that are symmetrical with respect to axes I and Q.
When the signals of oscillator 13 are phase shifted by an angle c|) with respect to the carriers in quadrature, one obtains an effective constellation rotated by an angle c|) with respect to the nominal constellation P1-P4, as shown in FIG. 2A. In 60 addition, if the frequency of oscillator 13 differs from the frequency of the carrier, angle c|) increases, i.e., the effective constellation rotates, at a speed equal to the frequency difference between the carrier and the oscillator 13.
FIG. 2B represents the phase error variation c|) when this 65 phase difference is equal to AF. Signal cj) is a saw-tooth varying between -it/4 and +it/4 at a frequency equal to 4AF
(the effective constellation reaches its nominal condition at each quarter of turn).
If the frequency difference AF is low (within the passband of filter 19), the control signal of oscillator 13 follows the variation of signal c|) and rapidly adjusts the frequency of oscillator 13 so that signal c|) does not reach one of the limits -it/4 or +jt/4. In contrast, if the frequency difference AF is important (much higher than the cut-off frequency of filter 19), signal c|) varies so rapidly that the control signal of oscillator 13 cannot vary at the same speed. Then, signal c|) becomes a saw-tooth as represented in FIG. 2B, and the control signal of oscillator 13 establishes at the mean value, i.e. zero, of this saw-tooth signal. As a consequence, oscillator 13 is in a steady state but is set at an erroneous frequency.
To avoid this situation, lock detection circuits are used for directly analyzing signal c|) and for indicating a lock condition when the amplitude of signal c|) is between two thresholds. When signal c|) exceeds these thresholds, oscillator 13 is forced, for example, to scan through its frequency range until a signal c|) varying below these thresholds is obtained.
However, signal c|) is often excessively noisy, which does not allow it to be compared with a threshold.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a detector for detecting a locked condition of a demodulator, that is efficient even if the phase error signal c|) is excessively noisy.
To achieve this and other objects, the present invention provides a method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference areas when the demodulator is wrongly (i.e., incorrectly or erroneously) adjusted.
According to an embodiment of the invention, each of the reference areas is defined between two lines crossing the origin of the constellation plane.
According to an embodiment of the invention, the method is applied to QPSK demodulation. The lines are in the number of four with respective slopes of 2, lA, -lA, and -2.
The invention also relates to a circuit for detecting a locked condition of a QPSK demodulator, including two absolute value circuits respectively receiving two quadrature demodulated signals; a circuit for providing the maximum and minimum values of the outputs of the two absolute value circuits; means for enabling a counter according to the sign of the difference between the maximum value and the product of the minimum value by a factor higher than 1; and means for asserting a lock indication signal when the content of the counter reaches a predetermined value.
According to an embodiment of the present invention, the counter is an up/down counter whose counting mode is selected by the sign and whose highest significant bit constitutes the lock indication signal.
The foregoing and other objects, features, aspects and advantages of the invention will become apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1, above described, schematically represents a conventional QSPK demodulator;