Dual phased-locked loop structure having configurable intermediate frequency ...

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US006970030B1

(12) United States Patent

Huang et al.

(io) Patent No.: US 6,970,030 Bl (45) Date of Patent: Nov. 29,2005

(54) DUAL PHASED-LOCKED LOOP

STRUCTURE HAVING CONFIGURABLE
INTERMEDIATE FREQUENCY AND
REDUCED SUSCEPTIBILITY TO
INTERFERENCE

(75) Inventors: Yunteng Huang, Irvine, CA (US);

Ligang Zhang, Austin, TX (US); Axel
Thomsen, Austin, TX (US)

(73) Assignee: Silicon Laboratories, Inc., Austin, TX (US)

A PLL function may be implemented as a dual-loop structure having a first PLL circuit which generates an intermediate signal from the reference signal, and a second PLL circuit which generates an output signal from the intermediate signal. The intermediate signal frequency is preferably chosen at a value in which potential interference signals do not have much energy. The first loop preferably has low bandwidth to provide good input jitter attenuation, while second loop preferably has higher bandwidth to reduce phase noise of the output signal. The circuit preferably provides for a choice of several different intermediate frequencies to allow use where different intermediate frequencies may exist in each system. Moreover, in a system having two such dual-loop PLL circuits, each can be configured with a different intermediate frequency, so that interference from one to the other is reduced.

34 Claims, 8 Drawing Sheets