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United States Patent m
Yazdy et al.
 METHODS AND APPARATUS FOR
CONTROLLING BACK-TO-BACK BURST
READS JN A CACHE SYSTEM
 Inventors: Farid A. Yazdy, San Mateo; Michael J. Dhuey, Cupertino, both of Calif.
 Assignee: Apple Computer, Inc., Cupertino, Calif.
 Appl. No.: 212,081
 Filed: Mar. 14,1994
 Int. CI.6 G06F 12/08
 U.S. CI 395/467; 395/403; 395/494;
 Field of Search 395/400, 425,
395/467, 872, 449, 440, 444, 445, 250, 855, 403, 421.05, 421.03, 494; 364/200 MS File,
900 MS File
 References Cited
U.S. PATENT DOCUMENTS
4,794,523 12/1988 Adan et al 364/200
4,884,198 11/1989 Garner et al 364/200
4,912,630 3/1990 Cocheroft, Jr 395/425
5,126,975 6/1992 Handy et al 395/425
5,146,582 9/1992 Begun 395/500
5,261,071 11/1993 Lyon 395/467
5,265,053 11/1993 Naradone et al 365/193
5,293,603 3/1994 MacWilliams et al 395/425
5,303,364 4/1994 Mayer et al 395/467
5,339,399 8/1994 Lee et al 395/425
5,345,573 9/1994 Bowden, HI et al 395/400
5,353,423 10/1994 Hamid et al 395/425
FOREIGN PATENT DOCUMENTS 0325420 7/1989 European Pat. Off. .
i Iiiii ilium Iii urn Iiiii inn inn in urn inn nun m in nil
[ii] Patent Number: 5,603,007  Date of Patent: Feb. 11,1997
Primary Examiner—Eddie P. Chan
Assistant Examiner—Hiep T. Nguyen
Attorney, Agent, or Firm—Can, DeFilippo & Ferrell, LLP
Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processordirect data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.
5 Claims, 8 Drawing Sheets