United States Patent [»] [ill Patent Number: 4,983,958
Carrick  Date of Patent: Jan. 8, 1991
 VECTOR SELECTABLE
COORDINATE-ADDRESS ABLE DRAM
 Inventor: Paul Carrick, Los Gatos, Calif.
 Assignee: Intel Corporation, Santa Clara, Calif.
 Appl. No.: 149,710
 Filed: Jan. 29, 1988
 Int CI.' G09G 1/02
 VJS. CL 340/799; 340/798;
364/200; 364/255.1; 364/900; 364/955
 Field of Search 340/799, 798, 789, 724,
340/726, 744, 747, 750; 364/518, 521, 200 MS File, 255.1 MS File, 900 MS File, 955 MS File
 References Cited
U.S. PATENT DOCUMENTS
4,038,646 7/1977 Mehta 307/269
4,644,503 2/1987 Bantz et al 364/521
4,742,474 5/1988 Kiuerim 340/799 .
4,745,407 5/1988 Costello 340/799
4,766,431 8/1988 Kobayashi et al 340/799
4,773,026 9/1988 Talcahara et al 340/747
4,845,640 7/1989 Ballard et al 340/798
Primary Examiner—Jeffery A. Brier
Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor & Zafman
An improved memory organization system is described. The stored data is specially transformed so that a data bus can carry either a row or column vector of data equally well. The improved memory organization is contained in a computer system, where a computer processor is coupled to memory devices by a bus interface unit and a multiplex address bus to access vectors of data. The memory devices are enabled by the bus interface unit and a decoder which operate in combination to allow during each fetch that no more than one storage device per section of the data bus be enabled. Once a vector is fetched, it is sent through the data bus to the bus interface's barrel shifter where the data is properly transformed from its physical positioning to its logical positioning. The aligned vector is then sent to the computer processor. This invention is particularly well suited for manipulating pixel information. Slight variations on the present invention make it useful for both bit plane and packed pixel selectability. Other slight variations allow for arrays having three for more logical dimensions.
29 Claims, 8 Drawing Sheets