Programmable slew rate control circuit for output buffer

United States Patent [w]

Do et al.

US005859552A [ii] Patent Number: [45] Date of Patent:

5,859,552 Jan. 12, 1999

[54] PROGRAMMABLE SLEW RATE CONTROL CIRCUIT FOR OUTPUT BUFFER

[75] Inventors: Tuan P. Do, San Jose; Casimiro A.

Stascausky, Fremont, both of Calif.

[73] Assignee: LSI Logic Corporation, Milpitas,
Calif.

[21] Appl. No.: 904,743
[22] Filed: Aug. 1, 1997

Related U.S. Application Data

[63] Continuation of Ser. No. 539,985, Oct. 6, 1995, abandoned.

[51] Int. CI.6 H03H 11/26

[52] U.S. CI 327/170; 327/276; 327/281

[58] Field of Search 327/170, 108,

327/276, 281

[56] References Cited

U.S. PATENT DOCUMENTS

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A slew rate control circuit for an output circuit of an integrated circuit includes an input node for obtaining an input signal and an output node for providing an output signal. A first stage of the control circuit includes at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor are connected together to the input node. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. One or more subsequent stages of the control circuit each contain at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor in each one or more subsequent stages of the control circuit are connected together to a control node driven from the control terminals of the preceding stage through at least one inverter. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. The at least one inverters associated with the one or more subsequent stages of the control circuit are sized so as to provide a predetermined amount of delay therethrough. In a user-programmable embodiment, the control terminals of each transistor are selectively connectable to the input node or to the output of any one of the inverters via switching elements.

8 Claims, 4 Drawing Sheets