(54) UTILIZING CACHE INFORMATION TO
MANAGE MEMORY ACCESS AND CACHE
(75) Inventors: John Zedlewski, Cambridge, MA (US);
Carl Waldspurger, Palo Alto, CA (US)
(73) Assignee: VMware, Inc., Palo Alto, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 38 days.
(21) Appl.No.: 12/199,671
(22) Filed: Aug. 27, 2008
(65) Prior Publication Data
US 2009/0187713 Al Jul. 23, 2009
Related U.S. Application Data
(63) Continuation of application No. 11/410,474, filed on Apr. 24, 2006, now Pat. No. 7,434,002.
(51) Int. CI.
(52) U.S. CI 711/130; 711/167; 712/216;
717/151; 717/154; 717/159
(58) Field of Classification Search None
See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
Non-Final Office Action dated Feb. 11, 2008 in U.S. Appl. No. 11/410,477.
Response to Non-Final Office Action dated Feb. 11, 2008 in U.S. Appl.No. 11/410,477.
Final Office Action dated Nov. 13, 2008 in U.S. Appl. No. 11/410,477.
Response to Final Office Action dated Nov. 13, 2008 in U.S. Appl. No. 11/410,477.
* cited by examiner
Primary Examiner—Jack A Lane
A method and system of managing data access in a shared memory cache of a processor are disclosed. The method includes probing one or more memory addresses that map to a subset of the shared memory cache and sensing a plurality of events in the one or more memory addresses. Cache utilization information is then obtained by reading a hardware performance counter of the processor. The hardware performance counter is incremented based on the occurrence of the plurality of events. Based upon the cache utilization information, an occurrence of one of the plurality of events is reduced.
25 Claims, 8 Drawing Sheets