(12) United States Patent ao) Patent No.: Us 7,051,329 Bi
Boggs et al. (45) Date of Patent: May 23,2006
Page 2
(54) METHOD AND APPARATUS FOR MANAGING RESOURCES IN A MULTITHREADED PROCESSOR
(75) Inventors: Darrell D. Boggs, Aloha, OR (US); Shlomit Weiss, Haifa (IL)
(73) Assignee: Intel Corporation, Santa Clara, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/473,575
(22) Filed: Dec. 28, 1999
Related U.S. Application Data
(63) Continuation-in-part of application No. 09/458,544, filed on Dec. 29, 1999, now Pat. No. 6,496,925.
OTHER PUBLICATIONS
Mendelson A. et al., "Design Alternatives of Multithreaded Architecture", International Journal of Parallel Programming, US, Plenum Press, New York, Jun. 3, 1999, pp. 161-193, vol. 27, No. 3, Plenum Publishing Corp. Farrens, M.K., et al., "Strategies for Achieving Improved Processor Throughput", Proceedings of the Annual International Symposium on Computer Architecture, May 1991, pp 362-369, vol. SYMP. 18.
R. Guru Prasadh, et al., A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture, 1991, pp 184-191, National Science Foundation and Cray Research Incorporated.
(Continued)
Primary Examiner—Meng-Al T. An
Assistant Examiner—Lilian Vo
(74) Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor & Zafman LLP
Lee et al.
Colwell et al.
Novak et al.
Fung
Sollars
Saito et al.
Cheong et al.
Paul
Flynn et al.
Paul
Borkenhagen et al.
Levy et al.
Kimura et al.
Gilmour et al.
Akkary et al
Borkenhagen et al.
Nation et al.
Akkary et al
Flynn
Rodgers et al
Rodgers et al
Levy et al
Gorishek et al
Nemirovsky et al.
Merchant et al
Smith et al
712/239
713/601 712/244 712/217 712/227 ... 712/7 712/219 712/218
Robert A. Iannucci, et al., Multithreaded Computer Architecture: A Summary of the State of the Art, pp 167-200, Kluwer Academic Publishers, Boston/London/Dordrecht.
Proceedings, The 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp 191-202, ACM SIGARCH, IEEE Computer Society, TCCA, Philadelphia, Pennsylvania.
Proceedings, The 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp 203-212, ACM SIGARCH, IEEE Computer Society, TCCA, Philadelphia, Pennsylvania.
Dennis Lee, et al. & Brad Calder, et al., Instruction Cache Fetch Policiess for Speculative Execution, pp 1-11, Depart mant of Computer Science.
Simon W. Moore, Multithreaded Processor Design, 1996, pp 1-141, Kluwer Academic Publishers, Boston/Dordrecht/ London.
Peter Song, Multithreading Comes of Age, Jul. 14, 1997, pp 13-18, Microdesign Resources.
Ruedeiger R. Asche, Multithreading for Rookies, Jul. 31, 1998, pp 1-15, Microsoft Developers Network Technology Group.
IEEE Computer Society Technical Committee on Computer Architecture, Second International Symposium on HighPerformance Computer Architecture, Feb. 3-7, 1996, pp291-301.
Dongwook Kim, Joonwon Lee, Seungkyu Park, A partitioned on-chip virtual cache for fast processors, Journal of Systems Architecture 43, 1997, pp 519-531, Elsevier, South Korea.
* cited by examiner
|
