United States Patent [w]
Hesson et al.
US005884061A [ii] Patent Number: 5,884,061  Date of Patent: *Mar. 16, 1999
 APPARATUS TO PERFORM SOURCE OPERAND DEPENDENCY ANALYSIS PERFORM REGISTER RENAMING AND PROVIDE RAPID PIPELINE RECOVERY FOR A MICROPROCESSOR CAPABLE OF ISSUING AND EXECUTING MULTIPLE INSTRUCTIONS OUT-OF-ORDER IN A SINGLE PROCESSOR CYCLE
 Inventors: James Henry Hesson; Jay LeBlanc;
Stephen J. Ciavaglia; Walter Thomas
Esling; Pamela Anne Wilcox, all ol
Chittenden County, Vt.
International Business Machines
Corporation, Armonk, N.Y.
The term ol this patent shall not extend beyond the expiration date ol Pat. No. 5,625,789.
 Appl. No.: 797,392
 Filed: May 1, 1995
Related U.S. Application Data
 Division of Ser. No. 328,184, Oct. 24, 1994, Pat. No. 5,625,789.
 Int. CI.6 G06F 9/34
 U.S. CI 395/393
 Field of Search 395/393, 394,
An apparatus performs source operand dependency analysis, perform register renaming and provide rapid pipeline recovery for a microprocessor capable of issuing and executing multiple instructions out-of-order in a single machine cycle. The apparatus first provides an enhanced means for rapid pipeline recovery due to a mispredicted branch or other store/load conflict or unsupported store/load forward circumstances. Second, the apparatus provides an improved instruction scheduling means wherein the oldest instructions that have all of their dependencies resolved are executed first. Third, the apparatus provides a means for enabling any execution or memory access instruction to execute out-oforder. Fourth, the apparatus provides a means for handling precise recovery of interrupts when processing instructions in out-of-order sequence.
4 Claims, 6 Drawing Sheets