SYSTEM AND METHOD FOR ERROR
LOCATION IN PRINTED WIRE
ASSEMBLIES BY EXTERNAL POWER ON
SELF TEST (POST) COMMANDS
 Inventor: James S. Bell, Cedar Park, Tex.
 Assignee: Dell USA, L.P., Austin, Tex.
 Appl. No.: 279,759
 Filed: Jul. 22, 1994
 Int. CI.6 G06F 11/34
 U.S. CI 395/183.12; 371/48
 Field of Search 395/575, 183.01,
395/183.07, 183.12; 371/16.5, 22.5, 15.1, 18, 25.1, 29.1
 References Cited
U.S. PATENT DOCUMENTS
4,620,302 10/1986 Binoeder et al 371/25.1
5,245,615 9/1993 Treu 311/16.5
5,371,884 12/1994 Ross 395/575
Ron White "How Computers Work" pp. 5-11, 1993.
Primary Examiner—Robert W. Beausoliel, Jr.
Assistant Examiner—Albert T. Decady
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US005535330A [ii] Patent Number: 5,535,330  Date of Patent: Jul. 9,1996
Attorney, Agent, or Firm—Henry N. Garrana; Mark P. Kahler; Michelle M. Turner
A system for detecting and locating errors in printed wire assemblies contained in a device with capabilities of performing a power on self test (POST) comprised of testing subroutines. The system monitors the device during execution of the POST. If a run error occurs during the POST, the system, through its monitoring, receives an indication of the run error. The system then delivers to the device a command, external to the POST routine, which directs the POST routine to thereafter separately execute each of the testing subroutines of the POST. If a run error occurs in any testing subroutine as it is being separately executed, a signal indicative of the run error and particular testing subroutine in which it occurred is sent to the system. The system, in this manner, may track a particular printed wire assembly and, with information about where within the printed wire assembly execution steps of the particular testing subroutine occur, determine the source within the printed wire assembly of the failure which caused the run error.