(54) ARITHMETIC UNIT AND DATA PROCESSING UNIT
(75) Inventors: Masahiro Ohashi, Fukuoka (JP); Mana Hamada, Fukuoka (JP); Tomonori Yonezawa, Fukuoka (JP); Shunichi Kurohmaru, Fukuoka (JP); Yasuo Kouhashi, Fukuoka (JP); Masatoshi Matsuo, Fukuoka (JP); Masayoshi Toujima, Fukuoka (JP)
(73) Assignee: Matsushita Electric Industrial Co., Ltd., Osaka (JP)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/978,204
(22) Filed: Oct. 17, 2001
(65) Prior Publication Data
US 2002/0026466 Al Feb. 28, 2002
Related U.S. Application Data
(62) Division of application No. 09/201,720, filed on Nov. 30, 1998, now Pat. No. 6,332,152.
(30) Foreign Application Priority Data
Dec. 2, 1997 (IP) 9-331417
(51) Int. C I. G06F 7/38
(52) U.S. CI 708/490; 708/671
(58) Field of Search 708/490, 523,
708/524, 525, 671; 341/67
(56) References Cited
U.S. PATENT DOCUMENTS 3,935,379 A 1/1976 Thornburg et al.
For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.
15 Claims, 17 Drawing Sheets