(12) United States Patent ao) Patent No.: Us 7,774,585 B2
Ober et al. (45) Date of Patent: Aug. 10,2010
(54) INTERRUPT AND TRAP HANDLING IN AN
EMBEDDED MULTI-THREAD PROCESSOR
TO AVOID PRIORITY INVERSION AND
MAINTAIN REAL-TIME OPERATION
(75) Inventors: Robert E. Ober, San Jose, CA (US);
Roger D.Arnold, Sunnyvale, CA (US);
Daniel F. Martin, Mountain View, CA
(US); Erik K. Norden, Unterhaching
(73) Assignee: Infineon Technologies AG, Neubiberg
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 189 days.
(21) Appl.No.: 10/712,473
(22) Filed: Nov. 12, 2003
(65) Prior Publication Data
US 2005/0102458 Al May 12, 2005
(51) Int. CI.
G06F 9/00 (2006.01)
(52) U.S. CI 712/244
(58) Field of Classification Search 712/244
See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS 5,197,138 A * 3/1993 Hobbs et al 712/222
A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a priority higher than the interrupt priority value, priority inversion can be avoided. Switching to the same thread before any interrupt servicing, and disabling interrupts and thread switching during interrupt servicing can simplify the interrupt handling logic. By storing trap background data for traps and servicing traps only in their originating threads, trap traceability can be preserved. By disabling interrupts and thread switching during trap servicing, unintended trap re-entrancy and servicing disruption can be prevented.
40 Claims, 9 Drawing Sheets