(i9) United States
(12) Patent Application Publication
Yang et al.
(io) Pub. No.: US 2008/0179667 Al (43) Pub. Date: Jul. 31, 2008
(54) SUB-LITHOGRAPHIC GATE LENGTH
TRANSISTOR USING SELF-ASSEMBLING
(75) Inventors: Haining S. Yang, Wappingers Falls, NY (US); Wai-Kin Li, Beacon, NY (US)
SCULLY, SCOTT, MURPHY & PRESSER, P.C. 400 GARDEN CITY PLAZA, Suite 300 GARDEN CITY, NY 11530
(73) Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,
Armonk, NY (US)
(21) Appl.No.: 12/099,435
(22) Filed: Apr. 8, 2008
Related U.S. Application Data
(62) Division of application No. 11/552,641, filed on Oct. 25, 2006, now Pat. No. 7,384,852.
(51) Int. CI.
H01L 29/76 (2006.01)
(52) U.S. CI 257/330; 257/351; 257/E29.226
A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.