[54] SYNCHRONOUS SRAM HAVING PIPELINED ENABLE
[75] Inventor: J. Thomas Pawlowski. Boise, Id.
[73] Assignee: Micron Technology, Inc.. Boise. Id.
[21] Appl. No.: 825,963
[22] Filed: Apr. 4, 1997
Related U.S. Application Data
[63] Continuation of Ser. No. 566,719, Dec. 4,1995, abandoned, which is a continuation-in-part of Ser. No. 540,581, Oct 5, 1995, abandoned, which is a continuation-in-part of Ser. No. 391,725, Feb. 21, 1995.
[51] Int CI.6 G06F9/38
[52] U.S. CI 711/169; 711/104; 395/855;
395/881; 365/230.01; 365/189.05; 365/233
[58] Field of Search 395/855. 881;
365/230.01. 189.05. 233; 711/104, 169
[56] References Cited
U.S. PATENT DOCUMENTS
4.141,068 2/1979 Mager et al. .
4^31,105 10/1980 Schuller et al. .
4,912,630 3/1990 Cochcroft, Jr. .
5,126,975 6/1992 Handy et al. .
5,491,663 2/1996 Teel 365/189.05
5,550,783 8/1996 Stephens, Jr. et al 365/233
OTHER PUBLICATIONS
Hitachi America, Ltd.. Semiconductor & LC. Division. "Hitachi's Synchronous Burst. Pipelined 1Mbit (32Kx32) SRAM Meets Industry Demand for Economical, Fast Cache Memory Devices for Pentium PCs", Mar. 13, 1995.
Primary Examiner—Tod R. Swann
Assistant Examiner—J. Peikari
Attorney, Agent, or Firm—Wells, St. John, Roberts, Gregory & Matkin. PS.
[57] ABSTRACT
A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean function of the chip enable signals; an enable register having an input connected to the chip enable and select logic for temporarily storing the SRAM core enable signal, and having an output; a pipelined enable register coupled between the enable register and the SRAM core for temporarily storing the SRAM core enable signal and delaying propagation of the core enable signal to the SRAM core; and pipelining logic coupled to at least one of the three chip enable inputs to permit pipelining operation of the synchronous burst SRAM device.
22 Claims, 7 Drawing Sheets
