(54) USE OF TA-CAPPED METAL LINE TO IMPROVE FORMATION OF MEMORY ELEMENT FILMS
(75) Inventors: Steven C. Avanzino, Cupertino, CA (US); Amit P. Marathe, Milpitas, CA (US)
(73) Assignees: Advanced Micro Devices, Inc.,
Sunnyvale, CA (US); Spansion LLC,
Sunnyvale, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 9 days.
(21) Appl. No.: 11/033,653
(22) Filed: Jan. 12, 2005
(51) Int. CI.
H01L 21/44 (2006.01)
(52) U.S. CI 438/685; 438/99; 438/597;
(58) Field of Classification Search 438/82,
438/99, 648, 685, 687, 692, 584, 597, 652, 438/653, FOR 111, FOR 406 See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
Disclosed are methods for deposition of improved memory element films for semiconductor devices. The methods involve providing a hard mask over an upper surface of a metal line of a semiconductor substrate where vias are to be placed, recess etching the mask substantially in all upper surfaces except where vias are to be placed, depositing a Ta-containing capping layer over substantially all the metal line surfaces except the surface where vias are to be placed, polishing the Ta-containing capping layer to produce a damascened Ta-containing cap while exposing the metal line at the via forming surface, depositing a dielectric layer, patterning the dielectric layer to form a via to expose a portion of the metal line, and depositing memory element films. The improved Ta—Cu interface of the subject invention mitigates and/or eliminates lateral growth of memory element films and copper voiding under the dielectric layer at the top surface of the metal line, and thereby enhances reliability and performance of semiconductor devices.
22 Claims, 9 Drawing Sheets