(54) MULTI-THREAD PARALLEL SEGMENT SCAN SIMULATION OF CHIP ELEMENT PERFORMANCE
(75) Inventors: Wei-Yi Xiao, Poughkeepsie, NY (US);
Dean G. Blair, Bloomington, NY (US);
Thomas Ruane, Poughkeepsie, NY
(US); William Lewis, Poughkeepsie, NY
(73) Assignee: International Business Machiens
Corporation, Armonk, NY (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 484 days.
This patent is subject to a terminal disclaimer.
(21) Appl.No.: 11/040,140
(22) Filed: Jan. 21, 2005
(65) Prior Publication Data
US 2006/0168497 Al Jul. 27, 2006
(51) Int. CI.
G01R 31/28 (2006.01)
G06F 7/02 (2006.01)
(52) U.S. CI 714/741; 714/726; 714/736;
(58) Field of Classification Search 714/762,
714/726-727, 729, 735-736, 799, 819, 741, 714/724; 716/4 See application file for complete search history.
A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first "snap shot" of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another "snap shot" of scan ring data is taken. The "snap shots" are compared and if both of the "snap shots" are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two "snap shots," it becomes necessary to locate the broken spot within the large number of scan latches.
8 Claims, 7 Drawing Sheets