METHOD AND STRUCTURE FOR
PROVIDING ESD PROTECTION FOR
SILICON ON INSULATOR INTEGRATED
 Inventors: David R. Staab, San Jose; Sheau-Suey Li, Cupertino, both of Calif.
 Assignee: Xilinx, Inc., San Jose, Calif.
 Appl. No.: 376,163
 Filed: Jan. 20, 1995
 Int. CI.6 H02H 9/00
 U.S. CI 361/56; 361/91; 361/111
 Field of Search 361/56, 58, 91,
361/117, 118, 127, 111
 References Cited
U.S. PATENT DOCUMENTS
4,037,140 7/1977 Eaton, Jr. 361/56
4,282,556 8/1981 Ipri 361/56
4,794,437 12/1988 Palumbo 357/23.13
4,989,057 1/1991 Lu 357/23.7
4,996,626 2/1991 Say 361/91
5,041,889 8/1991 Kriedt et al 357/23.13
5,124,877 6/1992 Graham 361/212
5,210,442 5/1993 Ishimoto 257/679
5,223,444 6/1993 Mosseretal 437/21
5,264,723 11/1993 Strauss 257/532
5,283,449 2/1994 Ooka 257/204
5,311,391 5/1994 Dungan et al 361/56
FOREIGN PATENT DOCUMENTS
58-222573 4/1984 Japan H01L 29/78
Palumbo, William and M. Patrick Dugan, "Design and Characterication of Input Protection Networks For CMOS/ SOS Applications," EOS/ESD Symposium Proceedings, 1986, pp. 182-187.
Whitehead, J. P. and N. N. Duncan, "Design and Evaluation of CMOS SOS On-Chip Input Protection Circuits," GEC Research Ltd., United Kingdom (date unknown) pp. 4.2.1 through 4.3.
Chan et al., "Comparison of ESD Protection Capability of
SOI and BULK CMOS Output Buffers," IEEE/RPS, Catalog
No. 94CH3332-4, 1994, pp. 292-298.
Cohen, Seymour and Gregory Caswell, "An Improved Input
Protection Circuit for C-MOS/SOS Arrays," IEEE Trans, on
Electron Devices, vol. Ed.25, No. 8, Aug., 1975, pp.
Primary Examiner—Jeffrey A. Gaffin
Assistant Examiner—Stephen Jackson
Attorney, Agent, or Firm—Skjerven, Morrill, MacPherson,
Franklin & Friel; Jeanette S. Harms
A method and structure for providing ESD protection for Silicon-On-Insulator (SOI) integrated circuits. The ESD protection circuit includes an electrically conductive pad and first conductor segment fabricated over an insulating layer. The first conductor segment connects the pad directly to a first node, without an intervening input resistor. A first diode is fabricated over the insulating layer and connected between the first node and a first voltage supply rail. Similarly, a second diode is fabricated over the insulating layer and connected between the first node and a second voltage supply rail. Ballast resistors can be included in series with each of the diodes. A cross power supply clamp, also fabricated over the insulating layer, is connected between the first and second voltage supply rails. The first node of the ESD protection circuit is coupled to the SOI integrated circuit to be protected. The ESD protection circuit can be fabricated on a minimum number of silicon islands to improve local thermal spreading. Improved ESD protection is provided to input, output, and I/O pins of an SOI integrated circuit, while promoting high speed signal transfer between these pins and the integrated circuit.
37 Claims, 18 Drawing Sheets