(12) United States Patent ao) Patent No.: us 6,985,974 Bi
Medina (45) Date of Patent: Jan. 10,2006
U.S. Appl. No. 10/000,944.
* cited by examiner
Primary Examiner—Kim Huynh
Assistant Examiner—Mike Nguyen
A network device receives data packets from a network adaptor. A low latency memory has a first read/write performance. A high latency memory has a second read/write performance that is slower than the first read/write performance of the low latency memory. An interface controller uses an address check circuit and values stored in registers to determine whether a read or write operation relates to header portions of the data packets. The interface controller stores header portions of the data packets in the low latency memory and data portions of the data packets in the high latency memory. The registers include base address, buffer pool size, maximum individual buffer size, and header size registers. Alternately the registers include base address, mask, maximum individual buffer size, and header size registers.
34 Claims, 5 Drawing Sheets