General purpose sequence controller

United States Patent n*]

Nakao et al.

[54] GENERAL PURPOSE SEQUENCE CONTROLLER

[75] Inventors: Hisaji Nakao; Katutoshi Naruse;

Kazuhiko Hasegawa, all of Toyota;
Sadao Kawade; Yasufumi Tokura,
both of Kariya; Kazuo Matsuno,
Gifu, all of Japan

173] Assignee: Toyoda Koki Kabushiki Kaisha,

Japan

[ * ] Notice: The portion of the term of this

patent subsequent to Sept. 3, 1991, has been disclaimed.

[22] Filed: June 13, 1974

[21] Appl. No.: 479,039

Related U.S. Application Data

[63] Continuation of Ser. No. 381,622, July 23, 1973, Pat. No. 3,832,696.

[30] Foreign Application Priority Data

July 31, 1972 Japan 47-76721

[52] U.S. CI 340/172.5

[51] Int. CI.2 G06F 3/00; G06F 9/06;

G06F 15/46

[58] Field of Search 340/172.5; 235/151.1 1;

178/6.7 R

[56] References Cited

UNITED STATES PATENTS

3,321,704 5/1967 Mann 324/68

3,351,912 11/1967 Collom et al 340/172.5

3,566,364 2/1971 Hauck 340/172.5

3,686,639 8/1972 Fletcher 340/172.5

[in 4,025,902

[45] * May 24, 1977

3,701,113 10/1972 Chace 340/172.5

3,731,280 5/1973 Shevlin 340/172.5

3,753,243 8/1973 Ricketts, Jr. et al 340/172.5

3^827,030 7/1974 Seipp 340/172.5

3,832,696 8/1974 Nakao 340/172.5

3,833,887 9/1974 Shevlin 340/172.5

3,849,765 11/1974 Hamano 340/172.5

OTHER PUBLICATIONS

Allen-Bradley Co. PMC-1750 Programmable Matrix Controller, Publication SD23, Aug. '72 (Previous Publication 4/71).

Primary Examiner—Gareth D. Shaw
Assistant Examiner—C. T. Bartz
Attorney, Agent, or Firm—Obion, Fisher, Spivak,
McClelland & Maier

[57] ABSTRACT

A general purpose sequence controller wherein a schematic electric circuit diagram comprising a ladder network of circuit lines disposed between two vertical bus lines is changeable and simulated by a special purpose control program. A logic operation circuit comprises first and second circuit means for examining an external input signal in accordance with examine commands of logical AND and OR functions, respectively, first and second memory means for temporarily memorizing the examined results of the first and second circuit means, respectively, third memory means for temporarily memorizing the application of the examine command of the logical OR function, and identifying circuit means for identifying the examined results of the logic operations in accordance with the contents of the first, second and third memory means.

8 Claims, 6 Drawing Figures

f- ONE COMMAND EXECUTING TIME

""'' bAWV- lfl¥«* It I Fl_ | '»CA # IrVrff'l/i

TCA, TOE, flT, m, ¥61l' 1 1 1' h 1''' f 'l h" f

(B) PULSE SIQNAL AT
TERMINAL CIS

(C) PULSE S/GA/AL AT
TERMINAL CLb

(D) PULSE SIGNAL A J
TERMINAL CL

NEXT COMMAKD EXECUTING TIME