(19) United States
(12) Patent Application Publication (io) Pub. No.: US 2002/0091979 Al
Cooke et al. (43) Pub. Date: Jul. 11,2002
(54) SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUITS
(75) Inventors: Laurence H. Cooke, Los Gatos, CA (US); Christopher K. Lennard,
Sunnyvale, CA (US)
LYON & LYON LLP
633 WEST FIFTH STREET
LOS ANGELES, CA 90071 (US)
(73) Assignee: Cadence Design Systems, Inc.
(21) Appl. No.: 09/888,054
(22) Filed: Jun. 22, 2001
Related U.S. Application Data
(63) Non-provisional ol provisional application No. 60/216,746, filed on Jul. 3, 2000, which is a nonprovisional of provisional application No. 60/214, 928, filed on Jun. 28, 2000, now abandoned.
A method of testing an integrated circuit including component blocks of random logic in a manufacturing environment is disclosed. The method includes the steps of performing built-in self tests, at least in part to test memory and data paths of the integrated circuit, performing diagnostics tests, at least in part to test the component blocks of random logic individually, performing stress tests using test vectors, at least in part to test the component blocks of random logic collectively; and performing scan-based tests of the integrated circuit, at least in part to test for structural faults in the integrated circuit.