US 7,890,693 B2 Feb. 15, 2011
(54) FLASH TRANSLATION LAYER APPARATUS
(75) Inventors: Cheng-chih Yang, Taipei (TW); Tei-wei Kuo, Taipei (TW); Chin-hsien Wu,
Taipei (TW)
(73) Assignee: Genesys Logic, Inc., Taipei (TW)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 549 days.
(21) Appl.No.: 12/018,346
(22) Filed: Jan. 23, 2008
(65) Prior Publication Data
US 2008/0183955 Al Jul. 31, 2008
(30) Foreign Application Priority Data
Jan. 25, 2007 (TW) 96102788 A
(51) Int. CI.
G06F12/00 (2006.01)
(52) U.S. CI 711/103; 711/118; 711/203;
711/206
(58) Field of Classification Search 711/103,
711/203, 206, 118 See application file for complete search history.
A flash translation layer apparatus is disclosed. The flash translation layer apparatus coupled to a flash memory and a reading and writing controller, respectively. The flash translation layer apparatus includes an instruction register, a logical address register, a data register, a first auxiliary controller, a microprocessor, an address converting unit, a second auxiliary controller, a flash address register and an adjustable translation layer unit. Furthermore, the adjustable translation layer unit regards the block as a unit for a coarse-grained address translation table and regards the pages as a unit for a fine-grained address translation table, respectively. Therefore, the present invention can provide capabilities of reducing the spaces and the times of a null data collection procedure and increasing the efficiency when a logical address corresponds to a physical address.
6 Claims, 7 Drawing Sheets
